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TC94A04AFD Datasheet(PDF) 19 Page - Toshiba Semiconductor |
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TC94A04AFD Datasheet(HTML) 19 Page - Toshiba Semiconductor |
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19 / 42 page ![]() TC94A04AF/AFD 2001-11-15 19 Command-45h (0100 0101): MSEQ D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 0 0 0 0 0 0 MSA2 MSA1 MSA0 Bit Name Description Value Operation D15 to D3 Fixed to 0 (zero) D2 to D0 MSA [2:0] Module sequential RAM first address 0h to 7h The address of the head to write in is set up. D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 MSEQ 9 MSEQ 8 MSEQ 7 MSEQ 6 MSEQ 5 MSEQ 4 MSEQ 3 MSEQ 2 MSEQ 1 MSEQ 0 Bit Name Description Value Operation D15 to D10 Fixed to 0 (zero) D9 to D0 MSEQ [9:0] Module sequential RAM data 000h to 3FFh The data written in module sequence RAM are set up. Data are sent continuously after transmitting the module sequence RAM head address (2 bytes). Enable a sequential write to RAM. 45h-MSEQ RAM address (2 bytes)-data (2 bytes)-data (2 bytes)-・・・・・・・・・- data (2 bytes) (module sequential RAM: 8 words) |
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