10

PS8689B

08/05/04

PI6CU877

PLL Clock Driver for

1.8V DDR2 Memory

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Figure 10. Dynamic Phase Offset

Figure 11. Time Delay Between Output Enable (OE) and Clock Output (Y, Y)

OE

Y/Y

Y

Y

50% VDD

50% VDD

tdis

50% VDD

50% VDD

ten

OE

Y

Y