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AD9925BBCZ Datasheet(PDF) 5 Page - Analog Devices

Part # AD9925BBCZ
Description  CCD Signal Processor with Vertical Driver and Precision Timing Generator
PDF  96 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD9925BBCZ Datasheet(HTML) 5 Page - Analog Devices

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AD9925
Rev. A | Page 5 of 96
VERTICAL DRIVER SPECIFICATIONS
VDVDD = 3.3 V, VH = 15 V, VM = 0 V, VL = −7.5 V, CL shown in load model, 25°C.
Table 3.
Parameter
Symbol
Min
Typ
Max
Unit
3-LEVEL OUTPUTS (V1, V2, V3A, V3B, V5A, V5B)
(Simplified Load Conditions, 6000 pF to Ground)
Delay Time, VL to VM and VM to VH
tPLM, tPMH
100
ns
Delay Time, VM to VL and VH to VM
tPML, tPHM
200
ns
Rise Time, VL to VM and VM to VH
tRLM, tRMH
500
ns
Fall Time, VM to VL and VH to VM
tFML, tFHM
500
ns
Output Currents
At −7.25 V
10.0
mA
At −0.25 V
−5.0
mA
At +0.25 V
5.0
mA
At +14.75 V
−7.2
mA
2-LEVEL OUTPUTS (V4, V6, V7, V8)
(Simplified Load Conditions, 6000 pF to Ground)
Delay Time, VL to VM
tPLM
100
ns
Delay Time, VM to VL
tPML
200
ns
Rise Time, VL to VM
tRLM
500
ns
Fall Time, VM to VL
tFML
500
ns
Output Currents
At −7.25 V
10.0
mA
At −0.25 V
−5.0
mA
SUBCK OUTPUT
(Simplified Load Conditions, 1000 pF to Ground)
Delay Time, VL to VH
tPLH
100
ns
Delay Time, VH to VL
tPHL
200
ns
Rise Time, VL to VH
tRLH
200
ns
Fall Time, VH to VL
tFHL
200
ns
Output Currents
At −7.25 V
5.4
mA
At +14.75 V
−4.0
mA
SERIAL VERTICAL CLOCK RESISTANCE
30
Ω
GND VERTICAL CLOCK RESISTANCE
10
Ω
V-DRIVER
INPUT
tRLM, tRMH, tRLH
50%
10%
90%
tPLM, tPMH, tPLH
V-DRIVER
OUTPUT
10%
50%
90%
tFML, tFHM, tFHL
tPML, tPHM, tPHL
Figure 2. Definition of V-Driver Timing Specifications



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