TSB41BA3APFP datasheet(35/66 Pages) TI

35 / 66 page

TSB41BA3A

IEEE 1394b THREEPORT CABLE TRANSCEIVER/ARBITER

SLLS618B − JUNE 2004 − REVISED AUGUST 2004

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

APPLICATION INFORMATION

bus reset (continued)

Therefore, in order to maintain consistent gap-counts throughout the bus, the following rules apply to the use

of the IBR bit, RHB bit, and gap-count in PHY register 1:

D Following the transmission of a PHY configuration packet, a bus reset must be initiated in order to verify

that all nodes have correctly updated their RHB bits and gap-count values, and to ensure that a subsequent

new connection to the bus causes the gap-count to be set to 63 on all nodes in the bus. If this bus reset is

initiated by setting the IBR bit to 1, then the RHB bit and gap-count register must also be loaded with the

correct values consistent with the just transmitted PHY configuration packet. In the TSB41BA3A, the RHB

bit and gap-count have been updated to their correct values upon the transmission of the PHY configuration

packet and so these values may first be read from register 1 and then rewritten.

D Other than to initiate the bus reset, which must follow the transmission of a PHY configuration packet,

whenever the IBR bit is set to 1 in order to initiate a bus reset, the gap-count value must also be set to 63

so as to be consistent with other nodes on the bus and the RHB bit must be maintained with its current value.

D The PHY register 1 must not be written to except to set the IBR bit. The RHB bit and gap-count must not

be written without also setting the IBR bit to 1.

D To avoid these problems all bus resets initiated by software must be initiated by writing the ISBR bit (bit 1

PHY register 0101b). Care must be taken to not change the value of any of the other writeable bits in this

be by means of the PHY configuration packet, which changes all nodes to the same gap count.

TSB41BA3APFP Datasheet(PDF) 35 Page - Texas Instruments