PIC16C781 datasheet(96/186 Pages) MICROCHIP

96 / 186 page

PIC16C781/782

DS41171A-page 94

Preliminary

 2001 Microchip Technology Inc.

12.1.2.2

Control Register CM2CON1

Comparator C2 has one additional feature: its output

can be synchronized to the Timer1 clock input. Setting

C2SYNC (CM2CON1<0>) synchronizes the output of

Comparator 2 to the falling edge of Timer 1’s clock input

(see Figure 12-1 and Register 12-3).

The CM2CON1 register also contains mirror copies of

both comparator outputs, MC1OUT and MC2OUT

(CM2CON1<7:6>). The ability to read both outputs

simultaneously from a single register eliminates the

timing skew of reading separate registers.

COMPARATOR C2 CONTROL REGISTER1 (CM2CON1: 11Bh)

R-0

U-0

R/W-0

MC1OUT MC2OUT

—

C2SYNC

bit 7

bit 0

bit 7

MC1OUT: Mirror Copy of C1OUT (CM1CON0<6>)

bit 6

MC2OUT: Mirror Copy of C2OUT (CM2CON0<6>)

bit 5-1

Unimplemented: Read as ’0’

bit 0

C2SYNC: C2 Output Synchronous Mode bit

= C2 output is synchronous to falling edge of TMR1 clock

= C2 output is asynchronous

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

- n = Value at POR

’1’ = Bit is set

’0’ = Bit is cleared

x = Bit is unknown

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