1 Features
• Ultra-low jitter BAW VCO based Ethernet clocks
– 13fs typical RMS jitter at 625MHz with 4MHz 1st
order high-pass filter (HPF)
– 24fs typical RMS jitter at 312.5MHz with 4MHz
1st order HPF
– 42fs typical/ 60fs maximum RMS jitter at
312.5MHz
– 47fs typical/ 65fs maximum RMS jitter at
156.25MHz
• Three high-performance Digital Phase Locked
Loops (DPLLs) with paired Analog Phase Locked
Loops (APLLs)
– Programmable DPLL loop bandwidth from
1mHz to 4kHz
– < 1ppt DCO frequency adjustment step size
• Two differential or single-ended DPLL inputs
– 1Hz (1PPS) to 800MHz input frequency
– Digital holdover and hitless switching
• 16 differential outputs with programmable HSDS,
AC-LVPECL, LVDS, and HSCL formats
– Up to 20 total frequency outputs when
configured with 6 LVCMOS frequency outputs
on OUT[1:0]_P/N, GPIO1, and GPIO2 and 14
differential outputs on OUT[15:0]_P/N
– 1Hz (1PPS) to 1250MHz output frequency with
programmable swing and common mode
– PCIe Gen 1 to 6 compliant
• I2C, 3-wire SPI, or 4-wire SPI
• –40°C to 85°C operating temperature

2 Applications
• Wired networking
– Inter/Intra DC interconnect
– Timing card, line card, fixed card (pizza box)
• SyncE (G.8262), SONET/SDH (Stratum 3/3E,
G.813, GR-1244, GR-253), IEEE-1588 PTP
secondary clock
• Jitter cleaning, wander attenuation, and reference
clock generation for 112G/224G PAM-4 SerDes
• 100G-800G data center switches, core routers,
edge routers, WLAN
• Data center and enterprise computing
– Smart Network Interface Card (NIC)
• Optical Transport Networks (OTN G.709)
• Broadband fixed line access
• Industrial
– Test and measurement
– Medical imaging

3 Description
The LMK5B33216 is a high-performance network
synchronizer and jitter cleaner designed to meet the
stringent requirements of ethernet-based networking
applications with < 5ns timing accuracy (ITU-T
G.8273.2 Class D).
The device integrates three DPLLs and three APLLs
to provide hitless switching and jitter attenuation
with programmable loop bandwidth (LBW) and one
external loop filter capacitor, maximizing flexibility and
ease of use.
APLL3 features an ultra-high performance PLL with
TI's proprietary Bulk Acoustic Wave (BAW) technology
in the VCO and can generate 312.5MHz output
clocks with 42fs typical RMS jitter (12kHz to 20MHz)
irrespective of the DPLL reference input frequency
and jitter characteristics. APLL2 and APLL1 feature
conventional LC VCOs to provide options for a
second or third frequency and/or synchronization
domain.
Reference validation circuitry monitors the DPLL
reference inputs and automatically performs a hitless
switch when the inputs are detected or lost. Zero-
Delay Mode (ZDM) provides control over the phase
relationship between inputs and outputs.
The device is fully programmable through I2C or SPI.
The integrated EEPROM can be used to customize
system start-up clocks. The device also features
factory default ROM profiles as fallback options.