ATSAMB11XR datasheet(39/87 Pages) MICROCHIP

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Pin Name

SPI Function

MOSI

Master Out Slave In (Data)

MISO

Master In Slave Out (Data)

9.3.2

SPI Interface Modes

The SPI Interface supports four standard modes as determined by the Clock Polarity (CPOL) and Clock

Phase (CPHA) settings. These modes are illustrated in Table 9-4 and Figure 9-1. The red lines in Figure

9-1 correspond to Clock Phase = 0 and the blue lines correspond to Clock Phase = 1.

Table 9-4. SPI Modes

Mode

CPOL

CPHA

Figure 9-1. SPI Clock Polarity and Clock Phase Timing

9.4

SPI Flash Master Interface

9.4.1

Description

The ATSAMB11-XR2100A and ATSAMB11-ZR210CA provide an SPI Master interface for accessing the

internal stacked SPI Flash memory. The TXD pin is same as the Master Output, Slave Input (MOSI), and

the RXD pin is the same as the Master Input, Slave Output (MISO). The SPI Master interface supports all

four standard modes of clock polarity and clock phase, as shown in Table 9-4. Internal stacked SPI Flash

memory is accessed by a processor programming commands to the SPI Master interface, which in turn

initiates SPI master access to the Flash.

ATSAMB11XR/ZR

Datasheet Preliminary

DS70005342A-page 39

ATSAMB11XR Datasheet(PDF) 39 Page - Microchip Technology