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ATSAMB11XR Datasheet(PDF) 57 Page - Microchip Technology |
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ATSAMB11XR Datasheet(HTML) 57 Page - Microchip Technology |
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57 / 87 page  Figure 10-8. SPI Master Timing Diagram Table 10-11. SPI Master Timing Parameters(1) Parameter Symbol Min. Units Max. Clock Output Frequency(2) fSCK 4 MHz Clock Low Pulse Width tWL 30 ns Clock High Pulse Width tWH 32 Clock Rise Time(3) tLH 7 Clock Fall Time(3) tHL 7 RXD Input Setup Time tISU 23 RXD Input Hold Time tIHD 0 SSN/TXD Output Delay(3) tODLY 0 12 Note: 1. Timing is applicable to all SPI modes 2. Maximum clock frequency specified is limited by the SPI Master interface internal design. The actual maximum clock frequency can be lower and depends on the specific PCB layout 3. Timing based on 15pF output loading 10.9.4 SPI Flash Master Timing The SPI Master Timing is provided in the following figure and table. ATSAMB11XR/ZR © 2017 Microchip Technology Inc. Datasheet Preliminary DS70005342A-page 57 |
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