AD8285CP-EBZ datasheet(6/28 Pages) AD

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Data Sheet

AD8285

Rev. B | Page 5 of 27

DIGITAL SPECIFICATIONS

AVDD18 = AVDD18ADC = 1.8 V, AVDD33 = AVDD33x1 = AVDD33REF = 3.3 V, DVDD18 = DVDD18CLK = 1.8 V, DVDD33SPI =

DVDD33CLK = DVDD33DRV = 3.3 V, 1.024 V internal ADC reference, fIN = 2.5 MHz, fSAMPLE = 72 MSPS, RS = 50 Ω, LNA + PGA gain =

34 dB, LPF cutoff = fSAMPLECH/4, full channel mode, 12-bit operation, temperature = −40°C to +105°C, unless otherwise noted.

Table 3.

Parameter2

Temperature

Min

Typ

Max

Unit

CLOCK INPUTS (CLK+, CLK−)

Logic Compliance

CMOS/LVDS/LVPECL

Differential Input Voltage3

Full

250

mV p-p

Input Common-Mode Voltage

Full

1.2

Differential Input Resistance

25°C

kΩ

Input Capacitance

25°C

1.5

LOGIC INPUTS (PDWN, SCLK, AUX, MUXA, ZSEL)

Logic 1 Voltage

Full

1.2

3.6

Logic 0 Voltage

Full

0.3

Input Resistance

25°C

kΩ

Input Capacitance

25°C

0.5

LOGIC INPUT (CS)

Logic 1 Voltage

Full

1.2

3.6

Logic 0 Voltage

Full

0.3

Input Resistance

25°C

kΩ

Input Capacitance

25°C

0.5

LOGIC INPUT (SDIO)

Logic 1 Voltage

Full

1.2

DVDD33x + 0.3

Logic 0 Voltage

Full

0.3

Input Resistance

25°C

kΩ

Input Capacitance

25°C

LOGIC OUTPUT (SDIO)4

Logic 1 Voltage (IOH = 800 μA)

Full

3.0

Logic 0 Voltage (IOL = 50 μA)

Full

0.3

LOGIC OUTPUT (Dx, DSYNC)

Logic 1 Voltage (IOH = 2 mA)

Full

3.0

Logic 0 Voltage (IOL = 2 mA)

Full

0.05

1 x stands for A, B, C, or D.

2 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions, and how these tests were completed.

3 Specified for LVDS and LVPECL only.

4 Specified for 13 SDIO pins sharing the same connection.

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