HT32F1655 datasheet(13/48 Pages) HOLTEK

13 / 48 page

Rev. 1.00

13 of �8

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3�-bit ARM® Cortex™-M3 MCU

HT3�F1656/HT3�F1655

The Universal Synchronous Asynchronous Receiver Transceiver, USART, provides a flexible

full duplex data exchange using synchronous or asynchronous transfer. The USART is used to

translate data between parallel and serial interfaces, and is commonly used for RS232 standard

communication. The USART peripheral function supports four types of interrupt including Line

Status Interrupt, Transmitter FIFO Empty Interrupt, Receiver Threshold Level Reaching Interrupt

and Time Out Interrupt. The USART module includes a 16-byte transmitter FIFO, (TX_FIFO) and

a 16-byte receiver FIFO (RX_FIFO). The software can detect a USART error status by reading the

Line Status Register, LSR. The status includes the type and the condition of transfer operations as

well as several error conditions resulting from Parity, Overrun, Framing and Break events.

Universal Asynchronous Receiver Transmitter – UART

▀ Asynchronous serial communication operating baud-rate up to 4.5 MHz

▀ Full duplex communication

▀ Fully programmable serial communication characteristics including:

● Word length: 7, 8, or 9-bit character

● Parity: Even, odd, or no-parity bit generation and detection

● Stop bit: 1 or 2 stop bit generation

● Bit order: LSB-first or MSB-first transfer

▀ Error detection: Parity, overrun, and frame error

▀ FIFO Depth: 16 x 9 bits for both receiver and transmitter

The Universal Asynchronous Receiver Transceiver, UART, provides a flexible full duplex data

exchange using asynchronous transfer. The UART is used to translate data between parallel and

serial interfaces, and is commonly used for RS232 standard communication. The UART peripheral

function supports four types of interrupt including Line Status Interrupt, Transmitter FIFO Empty

Interrupt, Receiver Threshold Level Reaching Interrupt and Time Out Interrupt. The UART

module includes a 16-byte transmitter FIFO, (TX_FIFO) and a 16-byte receiver FIFO (RX_

FIFO). The software can detect a UART error status by reading the Line Status Register, LSR. The

status includes the type and the condition of transfer operations as well as several error conditions

resulting from Parity, Overrun, Framing and Break events.

Smart Card Interface – SCI

▀ Supports ISO 7816-3 standard

▀ Character mode

▀ Single transmit buffer and single receive buffer

▀ 11-bit ETU (elementary time unit) counter

▀ 9-bit guard time counter

▀ 24-bit general purpose waiting time counter

▀ Parity generation and checking

▀ Automatic character retry on parity error detection in transmission and reception modes

The Smart Card Interface is compatible with the ISO 7816-3 standard. This interface includes

Card Insertion/Removal detection, SCI data transfer control logic and data buffers, internal

Timer Counters and corresponding control logic circuits to perform all the necessary Smart Card

operations. The Smart Card interface acts as a Smart Card Reader to facilitate communication

with the external Smart Card. The overall functions of the Smart Card interface are controlled

by a series of registers including control and status registers together with several corresponding

interrupts which are generated to get the attention of the microcontroller for SCI transfer status.

HT32F1655 Datasheet(PDF) 13 Page - Holtek Semiconductor Inc

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