SL28PCIe26

DOC#: SP-AP-0774 (Rev. 0.2)

Page 2 of 14

32-QFN Pin Definitions

promptly achieve optimum compliance and clock signal

integrity; historically, attainable typically through device and/or

board redesigns.

hard coded.

Features:

- > 4000 bits of configurations

- Can be configured through SMBus or hard coded

- Custom frequency sets

- Differential skew control on true or compliment or both

- Differential duty cycle control on true or compliment or both

- Differential amplitude control

- Differential slew rate control

- Program different spread profiles and modulation rates

Serial Data Interface

To enhance the flexibility and function of the clock synthesizer,

a two-signal serial interface is provided. Through the Serial

Data Interface, various device functions, such as individual

clock output buffers are individually enabled or disabled. The

registers associated with the Serial Data Interface initialize to

Pin No.

Name

Type

Description

1

VDD

PWR 3.3V Power Supply

2

VSS

GND

Ground

3

NC

NC

No Connect.

4

NC

NC

No Connect.

5

VDD

PWR 3.3V Power Supply

6

NC

NC

No Connect.

7

NC

NC

No Connect.

8

VSS

GND

Ground

9

VSS

GND

Ground

10

SRC0

O, DIF 100MHz True differential serial reference clock

11

SRC0#

O, DIF 100MHz Complement differential serial reference clock

12

VSS

GND

Ground

13

SRC1

O, DIF 100MHz True differential serial reference clock

14

SRC1#

O, DIF 100MHz Complement differential serial reference clock

15

VDD

PWR 3.3V Power Supply

16

NC

NC

No Connect.

17

VDD

PWR 3.3V Power Supply

18

VDD

PWR 3.3V Power Supply

19

SRC2#

O, DIF 100MHz Complement differential serial reference clock

20

SRC2

O, DIF 100MHz True differential serial reference clock

21

VSS

GND

Ground

22

SRC3#

O, DIF 100MHz Complement differential serial reference clock

23

SRC3

O, DIF 100MHz True differential serial reference clock

24

VDD

PWR 3.3V Power Supply

25

CKPWRGD/PD#

I

3.3V LVTTT input pin. When PD# is asserted low, the device will power down.

26

VSS

GND

Ground

27

XOUT

O, SE 25MHz Crystal output, Float XOUT if using CLKIN (Clock Input)

28

XIN/CLKIN

I

25MHz Crystal input or 3.3V, 25MHz Clock Input

29

VDD

PWR 3.3V Power Supply

30

NC

NC

No Connect.

31

SDATA

I/O

SMBus compatible SDATA

32

SCLK

I

SMBus compatible SCLOCK