SL28PCIe26

DOC#: SP-AP-0774 (Rev. 0.2)

Page 8 of 14

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PD# (Power down) Clarification

The CKPWRGD/PD# pin is a dual-function pin. During initial

power up, the pin functions as CKPWRGD. Once CKPWRGD

has been sampled HIGH by the clock chip, the pin assumes

PD# functionality. The PD# pin is an asynchronous active

LOW input used to shut off all clocks cleanly before shutting

off power to the device. This signal is synchronized internally

to the device before powering down the clock synthesizer. PD#

is also an asynchronous input for powering up the system.

When PD# is asserted LOW, clocks are driven to a LOW value

and held before turning off the VCOs and the crystal oscillator.

PD# (Power down) Assertion

When PD is sampled HIGH by two consecutive rising edges

of SRCC, differential clocks must held LOW. When PD mode

is desired as the initial power on state, PD must be asserted

HIGH in less than 10

s after asserting CKPWRGD.

PD# Deassertion

The power up latency is less than 1.8 ms. This is the time from

the deassertion of the PD# pin or the ramping of the power

supply until the time that stable clocks are generated from the

clock chip. All differential outputs stopped in a three-state

condition, resulting from power down are driven high in less

than 300

s of PD# deassertion to a voltage greater than

200 mV. After the clock chip’s internal PLL is powered up and

locked, all outputs are enabled within a few clock cycles of

each clock. Figure 2 is an example showing the relationship of

clocks coming up.

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40

OTP_4

OTP_ID

Idenification for programmed device

30

OTP_3

21

OTP_2

10

OTP_1

01

OTP_0

Bit

@Pup

Name

Description

Table 4. Output Driver Status

All Differential Clocks

Clock

Clock#

PD# = 0 (Power down)

Low

Low

Figure 1. Power down Assertion Timing Waveform

Figure 2. Power down Deassertion Timing Waveform