MCP6S21 datasheet(18/43 Pages) MICROCHIP

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MCP6S21/2/6/8

DS21117A-page 18

 2003 Microchip Technology Inc.

5.0

DIGITAL FUNCTIONS

The MCP6S21/2/6/8 PGAs use a standard SPI com-

patible serial interface to receive instructions from a

controller. This interface is configured to allow daisy

chaining with other SPI devices. There is an internal

POR (Power On Reset) that resets the registers under

low power conditions.

5.1

SPI Timing

Chip Select (CS) toggles low to initiate communication

with these devices. The first byte of each SI word (two

bytes long) is the instruction byte, which goes into the

Instruction Register. The Instruction Register points the

second byte to its destination. In a typical application,

CS is raised after one word (16 bits) to implement the

desired changes. Section 5.3, “Registers”, covers

applications using multiple 16-bit words. SO goes low

after CS goes high; it has a push-pull output that does

not go into a high-Z state.

The MCP6S21/2/6/8 devices operate in SPI Modes 0,0

and 1,1. In 0,0 mode, the clock idles in the low state

(Figure 5-1) and, in 1,1 mode, the clock idles in the high

state (Figure 5-2). In both modes, SI data is loaded into

the PGA on the rising edge of SCK and SO data is

clocked out on the falling edge of SCK. In 0,0 mode, the

falling edge of CS also acts as the first falling edge of

SCK (see Figure 5-1). There must be multiples of 16

clocks (SCK) while CS is low or commands will abort

(see Section 5.3, “Registers”).

FIGURE 5-1:

Serial bus sequence for the PGA; SPI 0,0 mode (see Figure 1-5).

FIGURE 5-2:

Serial bus sequence for the PGA; SPI 1,1 mode (see Figure 1-6).

3456

SCK

Instruction Byte

Data Byte

(first 16 bits out are always zeros)

SCK

Instruction Byte

Data Byte

(first 16 bits out are always zeros)

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