S70FS01GS datasheet(49/141 Pages) CYPRESS

49 / 141 page

S70FS01GS

Document Number: 002-03833 Rev. *C

Page 49 of 141

Write In Progress (WIP) SR1V[0]

: Indicates whether the device is performing a program, write, erase operation, or any other

operation, during which a new operation command will be ignored. When the bit is set to a “1” the device is busy performing an

operation. While WIP is “1”, only Read Status (RDSR1 or RDSR2), Read Any Register (RDAR), Erase Suspend (ERSP), Program

Suspend (PGSP), Clear Status Register (CLSR), and Software Reset (RESET) commands are accepted. ERSP and PGSP will only

be accepted if memory array erase or program operations are in progress. The status register E_ERR and P_ERR bits are updated

while WIP =1. When P_ERR or E_ERR bits are set to one, the WIP bit will remain set to one indicating the device remains busy and

unable to receive new operation commands. A Clear Status Register (CLSR) command must be received to return the device to

standby mode. When the WIP bit is cleared to 0 no operation is in progress. This is a read-only bit.

7.7.2

Status Register 2 Volatile (SR2V)

Related Commands: Read Any Register (RDAR 65h). Status Register 2 does not have user programmable non-volatile bits, all

defined bits are volatile read only status. The default state of these bits are set by hardware.

Erase Status (ESTAT) SR2V[2]:

The Erase Status bit indicates whether the sector, selected by an immediately preceding Erase

status command, completed the last erase command on that sector. The Erase Status command must be issued immediately before

reading SR2V to get valid erase status. Reading SR2V during a program or erase suspend does not provide valid erase status. The

erase status bit can be used by system software to detect any sector that failed its last erase operation. This can be used to detect

erase operations failed due to loss of power during the erase operation.

Erase Suspend (ES) SR2V[1]

: The Erase Suspend bit is used to determine when the device is in Erase Suspend mode. This is a

status bit that cannot be written by the user. When Erase Suspend bit is set to “1”, the device is in erase suspend mode. When Erase

Suspend bit is cleared to “0”, the device is not in erase suspend mode. Refer to Section 9.6.6 Erase or Program Suspend (EPS 85h,

75h) on page 101 for details about the Erase Suspend/Resume commands.

Program Suspend (PS) SR2V[0]:

The Program Suspend bit is used to determine when the device is in Program Suspend mode.

This is a status bit that cannot be written by the user. When Program Suspend bit is set to “1”, the device is in program suspend

mode. When the Program Suspend bit is cleared to “0”, the device is not in program suspend mode. Refer to Section 9.6.6 Erase or

Program Suspend (EPS 85h, 75h) on page 101 for details.

Table 7.7

Status Register-2 Volatile (SR2V)

Bits

Field Name

Function

Type

Default State

Description

RFU

Reserved

Reserved for Future Use

RFU

Reserved

Reserved for Future Use

RFU

Reserved

Reserved for Future Use

RFU

Reserved

Reserved for Future Use

RFU

Reserved

Reserved for Future Use

ESTAT

Erase Status

Volatile

Read Only

1 = Sector Erase Status command result = Erase

Completed

0 = Sector Erase Status command result = Erase Not

Completed

Erase Suspend

Volatile

Read Only

1 = In erase suspend mode.

0 = Not in erase suspend mode.

Program Suspend

Volatile

Read Only

1 = In program suspend mode.

0 = Not in program suspend mode.

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