Kawasaki USB device

KL5KUSB201

Copyright © 2002 Kawasaki Microelectronics Inc. Kawasaki LSI Inc. All rights reserved.

7. SIE Bus Timing

7.1 SIE Bus Output Timing

Timing diagram of USB data output to SIE bus is shown in Figure 7-1. SIE bus direction

is output in default. The LSI asserts RXACT to notice output of data to the external SIE

logic. Valid data is indicated by RXVLD assertion. Odd byte of received USB data is

driven to the lower byte of SIE bus. If SIE output data is in odd byte length, the LSI

negates WDVLD at the final data valid phase to indicate that the last one is byte data.

Figure 7-1 SIE Bus Output Timing

CKOUT (O)

TXACT (I)

TXRDY (O)

RXACT (O)

RXVLD (O)

B1

B2

B3

B4

B5

7.2 SIE Bus Input Timing

Figure 7-2 shows the receive timing diagram of the LSI from SIE bus. External

SIE circuit asserts TXACT to notice the LSI to get data on SIE bus. When TXRDY is

asserted, valid data is latched by the LSI. If data from SIE is odd byte length, SIE

negates WDVLD at the final data stage like the case in SIE bus output timing.

Please note that in Figure 7-2, a case of even byte length data is depicted.