CS43L36 datasheet(18/89 Pages) CIRRUS

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DS1081F3

CS43L36

3 Characteristics and Specifications

Fall time of SCL and SDA

Standard Mode

Fast Mode

Fast Mode Plus

tFC

—

300

120

Setup time for stop condition

tSUSP

260

—

SDA setup time to SCL rising

tSUD

—

SDA input hold time from SCL falling 4

tHDDI

0—

Output data valid (Data/Ack) 5

Standard Mode

Fast Mode

Fast Mode Plus

tVDDO

—

3450

900

450

Bus free time between transmissions

tBUF

500

—

SDA bus capacitance

Fast Mode Plus

Standard Mode, Fast Mode

—

550

400

SCL/SDA pull-up resistance 1

VL = 1.2 V

VL = 1.8 V

200

250

—



Switching time between RCO and PLL or SCLK 6

—

150

—

µs

1.The minimum RP value (see Fig. 2-1) is determined by using the maximum VL level, the minimum sink current strength of its respective output, and

the maximum low-level output voltage, VOL. The maximum RP value may be determined by how fast its associated signal must transition (e.g., the

lower the RP value, the faster the I2C bus can operate for a given bus load capacitance). See the I²C bus specification referenced in Section 13.

2.All timing is relative to thresholds specified in Table 3-14, VIL and VIH for input signals, and VOL and VOH for output signals.

3.I²C control-port timing

4.Data must be held long enough to bridge the SCL transition time, tF.

5.Time from falling edge of SCL until data output is valid.

6.The switch between RCO and either SCLK or PLL occurs upon setting/clearing SCLK_PRESENT (see p. 63) and sending the I2C stop condition.

SCLK_PRESENT transition (0 to 1 or 1 to 0) starts a

switch between RCO and the selected SCLK or PLL. An I2C stop condition is sent, after which

a wait time of at least 150

s is required before the next I2C transaction can begin using the newly selected clock.

Table 3-13. I2C Slave Port Characteristics (Cont.)

Test conditions (unless specified otherwise): Fig. 2-1 shows typical connections; Inputs: GNDA = GNDL = GNDCP = 0 V; all voltages with respect to

ground; min/max performance data taken with VL = 1.66–1.94 V (VL_SEL = VP) or VL = 1.1–1.3 V (VL_SEL = GNDD); inputs: Logic 0 = GNDA = 0 V,

Logic 1 = VL; TA = +25°C; SDA load capacitance equal to maximum value of CB = 400 pF; minimum SDA pull-up resistance, RP(min).1 Table 3-1

describes some parameters in detail. All specifications are valid for the signals at the pins of the CS43L36 with the specified load capacitance.

Parameter 2

Symbol 3

Minimum

Maximum

Unit

tBUF

tLOW

Stop

tHDDI

tSUD

tSUST

tRC

tHDST

tHIGH

tHDST

tFC

tSUSP

Start

Repeated

Start

Stop

SDA

SCL

tVDDO

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