LP4061-02

Mar.-2017

www.lowpowersemi.com

Page 6 of 7

Preliminary Datasheet

LP4061

Under voltage Lockout (UVLO)

An internal under voltage lockout circuit monitors the input

rises above the under voltage lockout threshold .The UVLO

circuit has a built-in hysteresis of 200mV. Furthermore, to

protect against reverse current in the power MOSFET, the

to within 80mV of the battery voltage. If the UVLO comparator

is tripped, the charger will not come out of shutdown mode

Manual Shutdown

At any point in the charge cycle, the LP4061 can be put into

pin. This reduces the battery drain current to less than 2µA

and the supply current to less than 50µA. A new charge cycle

can be initiated by reconnecting the program resistor.

Automatic Recharge

Once the charge cycle is terminated, the LP4060A

continuously monitors the voltage on the BAT pin using a

restarts when the battery voltage falls below 4.05V (which

corresponds to approximately 80% to 90% battery capacity).

This ensures that the battery is kept at or near a fully charged

condition and eliminates the need for periodic charge cycle

initiations. CHRG output enters a strong pull-down state.

Power Dissipation

The conditions that cause the LP4061 to reduce charge

current through thermal feedback can be approximated by

considering the power dissipated in the IC. Nearly all of this

power dissipation is generated by the internal MOSFET—this

is calculated to be approximately:

current. The approximate ambient temperature at which the

thermal feedback begins to protect the IC is:

VCC Bypass Capacitor

Many types of capacitors can be used for input bypassing;

however, caution must be exercised when using multilayer

ceramic capacitors. Because of the self-resonant and high Q

characteristics of some types of ceramic capacitors, high

voltage transients can be generated under some start-up

conditions, such as connecting the charger input to a live

power source .Adding a 1.5Ω resistor in series with an X5R

ceramic capacitor will minimize start-up voltage transients.

Layout Considerations



Follow the PCB layout guidelines for optimal

performance of LP4061.



For the main current paths as indicated in bold lines,

keep their traces short and wide.



Put the input capacitor as close as possible to the device

pins (VCC and GND).



Connect all analog grounds to a command node and

then connect the command node to the power ground

behind the output capacitors.



Output not connect loading when charging.