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MPQ8616 Datasheet(PDF) 21 Page - Monolithic Power Systems

Part # MPQ8616
Description  High Efficiency, 6A/12A, 6V Synchronous Step-down Converter
PDF  29 Pages
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Manufacturer  MPS [Monolithic Power Systems]
Direct Link  http://www.monolithicpower.com
Logo MPS - Monolithic Power Systems

MPQ8616 Datasheet(HTML) 21 Page - Monolithic Power Systems

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MPQ8616, 6A/12A, 6V, SYNCHRONOUS STEP-DOWN CONVERTER
MPQ8616 Rev. 1.11
www.MonolithicPower.com
21
3/16/2016
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2016 MPS. All Rights Reserved.
in noise immunity. The magnitude of the VFB
ripple
doesn’t
affect
the
noise
immunity
directly.
Figure 3—Jitter in PWM Mode
Ramp with Large ESR Capacitor
In the case of POSCAP or other types of
capacitor with lager ESR is applied as output
capacitor, the ESR ripple dominates the output
ripple, and the slope on the FB is quite ESR
related. Figure 4 shows an equivalent circuit in
PWM mode with the HS-FET off and without an
external ramp circuit. Turn to application
information section for design steps with large
ESR capacitors.
R1
R2
ESR
POSCAP
SW
Vo
L
FB
Figure 4—Simplified Circuit in PWM Mode
without External Ramp Compensation
To realize the stability when no external ramp is
applied, usually the ESR value should be chosen
as follow:
SW
ON
ESR
OUT
tt
0.7
2
R
C

(3)
TSW is the switching period.
Ramp with Small ESR Capacitor
When the output capacitors are ceramic ones,
the ESR ripple is not high enough to stabilize the
system, and external ramp compensation is
needed. Skip to application information section
for design steps with small ESR caps.
R1
R2
Ceramic
SW
FB
Vo
L
R4
C4
IR4
IC4
IFB
R9
Figure 5—Simplified Circuit in PWM Mode
with External Ramp Compensation
In PWM mode, an equivalent circuit with HS-FET
off
and
the
use
of
an
external
ramp
compensation circuit (R4, C4) is simplified in
Figure 5. The external ramp is derived from the
inductor ripple current. If one chooses C4, R9,
R1 and R2 to meet the following condition:
12
9
SW
4
1
2
RR
11
R
2f
C
20
R
R





(4)
Where:
R4
C4
FB
C4
II
I
I

(5)
And the ramp on the VFB can then be estimated
as:
IN
O
12
RAMP
ON
44
1
2
9
VV
R//R
Vt
RC
R //R
R


 


(6)
The downward slope of the VFB ripple then
follows:
OUT
RAMP
SLOPE1
off
4
4
V
V
V
tR
C

(7)
As can be seen from equation 7, if there is
instability in PWM mode, we can reduce either
R4 or C4. If C4 can not be reduced further due to
limitation from equation 4, then we can only
reduce R4. For a stable PWM operation, the
Vslope1 should be design follow equation 8.
SW
ON
3
ESR
OUT
O
SLOPE1
OUT
OUT
sw
on
tt
RC
0.7 I
10
0.7
2
VV
2L C
t
t





(8)
Where Io is the load current.



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