MPQ8616, 6A/12A, 6V, SYNCHRONOUS STEP-DOWN CONVERTER

MPQ8616 Rev. 1.11

www.MonolithicPower.com

28

3/16/2016

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LAYOUT RECOMMENDATION

1. Four-layer layout is strongly recommended to

achieve better thermal performance.

2. Place at least 9 vias (10/20mil hole/diameter

size) right beneath the IC to get best

decoupling effect.

3. Place

10

or

more

vias

(10/25mil

hole/diameter size) each for input and GND

copper next to the VIN and PGND pin to

improve the thermal performance.

4. A 22uF (1206/1210) input cap C1B is

required on bottom layer, right beneath the

VIN/PGND vias to get best input decoupling

effect.

5. If VIN/PGND vias is not allowed beneath the

IC, a 22uF input cap with 1206/1210 package

(C1C) is required on the Top layer as

Figure17, connecting to VIN and PGND

copper directly, within 2mm of the IC edge.

6. A solid PGND layer is required to place on

the first inner layer, right below the IC layer.

7. The high current paths (GND, IN, and SW)

should be placed very close to the device

with short, direct and wide traces.

8. VCC decoupling capacitor (C5) should be as

close to the VCC pin as possible, connect its

GND net to PGND copper.

9. Connect all AGND signals together to AGND

pin at first, then Kelvin connect AGND to

PGND near the VCC decoupling capacitor(C5)

GND pad on Top layer. Keep AGND trace

20mil or wider.

10. The external feedback resistors should be

placed next to the FB pin. Make sure that

there is no via on the FB trace and away from

the switching node SW.

11. Keep the BST voltage path (BST, C3, Rbst

and SW) as short as possible.

12. Keep the Vout sense trace away from noise

signal, such as SW, VIN, etc. Put the Vout

sense point to a stable, quiet output point

close to Vout cap.

Schematic for PCB Layout Guide Line

Figure 16—PCB LAYOUT

<2mm

C1C

<2mm

VIN

PGND

Figure 17—VIN Decouple Capacitor