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SAFC161RI Datasheet(PDF) 8 Page - Siemens Semiconductor Group |
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SAFC161RI Datasheet(HTML) 8 Page - Siemens Semiconductor Group |
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8 / 60 page ![]() Semiconductor Group 8 1998-05-01 C161RI P4.0 – P4.6 24 – 30 24 ... 30 26 - 32 26 ... 32 I/O I/O O ... O Port 4 is a 7-bit bidirectional I/O port. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into high- impedance state. In case of an external bus configuration, Port 4 can be used to output the segment address lines: P4.0 A16 Least Significant Segment Addr. Line ... ... ... P4.6 A22 Most Significant Segment Addr. Line RD 31 33 O External Memory Read Strobe. RD is activated for every external instruction or data read access. WR/WRL 32 34 O External Memory Write Strobe. In WR-mode this pin is activated for every external data write access. In WRL-mode this pin is activated for low byte data write accesses on a 16- bit bus, and for every data write access on an 8-bit bus. See WRCFG in register SYSCON for mode selection. READY 33 35 I Ready Input. When the Ready function is enabled, a high level at this pin during an external memory access will force the insertion of memory cycle time waitstates until the pin returns to a low level. ALE 34 36 O Address Latch Enable Output. Can be used for latching the address into external memory or an address latch in the multiplexed bus modes. EA 35 37 I External Access Enable pin. A low level at this pin during and after Reset forces the C161RI to begin instruction execution out of external memory. A high level forces execution out of the internal ROM. The C161RI must have this pin tied to ‘0’. Note: This pin is expected to be used to accept the programming voltage for OTP versions of the C161RI. Pin Definitions and Functions (cont’d) Symbol Pin No. TQFP Pin No. MQFP Input Outp Function |
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