MP2953B – DIGITAL PWM CONTROLLER WITH PMBUS FOR VR12.5

MP2953B Rev. 1.01

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21

10/9/2015

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b) The VR latches if the input voltage is

above VIN_OV_FAULT_LIMIT.

c) The VR is warned if the input voltage is

below VIN_UV_WARNING_LIMIT.

Under Voltage: When the output voltage is

below VID – 300mV for a pre-set time, the VR

either latches off or re-starts depending on

the user selection via the PMBus.

Over Voltage:

a) When the output voltage is above VID +

300mV for a pre-set time, the VR latches

off (with all the low-side MOSFETs

turned on). It can be programmed to re-

start after the fault condition clears.

b) When the output voltage is above

Vout_Max + 400mV for another pre-set

time, the VR latches off (with all the low-

side MOSFETs turned on).

Reverse Voltage: All the low-side MOSFETs

turn off if the output voltage is below 30mV.

Over Current: When the total current is

above the OCP level for a pre-set time, the

VR latches off or re-starts.

Over-Temperature

Indicator

(VRHOT#,

Active Low): When the temperature is above

OTP_LIMIT,

the

VR

latches

until

the

temperature

falls

below

OTP_LIMIT-

OTP_HYS.

Fault# Signal (CFP): When Vin is above

VIN_OV_FAULT_LIMIT or the output voltage

is above Vout_Max +400mV, then Fault#

pulls low actively.

CML: The PMBus communication fault.

EEPROM Fault: The data in the EEPROM is

invalid.

All fault conditions can be monitored via the

PMBus.

OVP, OCP, and UVP modes have options of no

action, latch, retry, or hiccup mode. After the fault

condition clears, the MP2953B waits12.5ms

before attempting to re-start again. A 12.5ms

delay ensures a sufficiently low duty-cycle stress

rate to prevent regulator components from being

damaged by power cycling.

For

latched

protection

mode,

external

intervention is required to clear the latch before

the VR can re-start again. External intervention

includes the enable signal toggle, controller

power-supply recycle, or input-voltage supply

toggle.

The fault status is record in the registers. Once

triggered, the fault registers report faults even if

the fault condition no longer exists. Fault

registers may be cleared manually by issuing a

fault clear command, controller power-supply

cycle, or the enable signal toggle (either by EN or

command enable toggle).

The following is a brief description of each fault:

Over-Voltage Protection (OVP)

The OVP circuit monitors the output voltage for

an over-voltage condition. The over-voltage

signal generation is shown in Fig. 11.

VID

300mV

COMP

VDIFF

OV2

COMP

OV1

COMP

UV

COMP

RV

30mV

VOSEN

DAC

VOUT_MAX+400mV

FIGURE 11. OV, UV, and RV Signal Generation

There are two levels of over-voltage protection:

1. OVP2 (VID+300mV) and

2. OVP1 (VOUT_MAX + 400mV).

The OVP2 signal is blanked during the soft-start

and soft-shut down process to avoid a false

trigger by a pre-bias condition. Also, the OVP2

monitor is disabled during a VID decay transition.

It re-activates after finishing the VR settle re-

assertion transition.