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MP2953B Datasheet(PDF) 12 Page - Monolithic Power Systems |
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MP2953B Datasheet(HTML) 12 Page - Monolithic Power Systems |
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12 / 30 page ![]() MP2953B – DIGITAL PWM CONTROLLER WITH PMBUS FOR VR12.5 MP2953B Rev. 1.01 www.MonolithicPower.com 12 10/9/2015 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2015 MPS. All Rights Reserved. PIN FUNCTIONS Pin # Name I/O Description 24 VRFLT# O VR Fault. VRFLT# is an open-drain output. When Vin or Vout OVP occurs, VRFLT# is asserted to shut down the input power supply. 25 VRHOT# O Voltage Regulator Thermal Throttling Logic Output. VRHOT# is an open- drain output. VRHOT# pulls low actively if the monitored temperature exceeds the programmed VRHOT# temperature threshold. 26 VRRDY O VR Ready Output. VRRDY is an open-drain output that signals when the output voltage is outside of the proper operating range. A VTT rail is expected for pull up; however, some systems may pull up to a maximum voltage of 3.3V with an external pull-up circuit. 27 DGND I/O Digital Ground. 28 ALT_P# O Open-Drain Output that Asserts Low when a Warning has Occurred. 29 SDA_P I/O Data Signal between the PMBus Controller and the VID Controller. 30 SCL_P I Source Synchronous Clock from the PMBus Controller. 31 CCM O Forced CCM Operations Enable. CCM stays high in power state 0 and 1. It pulls low actively during PS2/3 to enable DCM operation. 32 PWM6 O 33 PWM5 O 34 PWM4 O 35 PWM3 O 36 PWM2 O 37 PWM1 O Tri-State Logic-Level PWM Outputs. Each output is connected to the input of Intelli-Phase’s PWM pin. The logic levels are 0V for low logic and 3.3V for high logic. The output is set to tri-state (High-Z) to shut down both the high-side MOSFET and the low-side MOSFET of Intelli-Phase. 38 VDD33 O 3.3V LDO Output for the Internal Digital Power Supply. Connect a 1µF bypass capacitor to digital ground. 39 EN I Enable Control for the Controller. 40 CS6 I Phase 6 Current Sense Inputs. Float CS of the unused phase. PAD AGND I/O Analog Ground. |
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