ISL5216 datasheet(13/65 Pages) RENESAS

13 / 65 page

ISL5216

FN6013 Rev.3.00

Page 13 of 65

July 13, 2007

Back End Data Routing

Back End Section

One back-end processing section is provided per channel.

Each back end section consists of a filter compute engine, a

FIFO/timer for evenly spacing samples (important when

implementing interpolation filters and resamplers), an AGC

and a cartesian-to-polar coordinate conversion block. A

block diagram showing the major functional blocks and data

routing is shown above. The data input to the back end

section is through the filter compute engine. There are two

other inputs to the filter compute engine, they are a data

recirculation path for cascading filters and a magnitude and

/dt feedback path for AM and FM filtering. There are seven

outputs from each back end processing section. These are I

and Q directly out of the filter compute engine (I2, Q2), I and

Q passed through the FIFO and AGC multipliers (I1, Q1),

magnitude (MAG), phase (or d

/dt), and the AGC gain

control value (GAIN). The I2/Q2 outputs are used when

cascading back end stages. The routing of signals within the

back end processing section is controlled by the filter

compute engine. The routing information is embedded in the

instruction bit fields used to define the digital filter being

implemented in the filter compute engine.

MAG: I

dphi/dt: Q

AGC

LOOP

FILTER

COMPUTE

ENGINE

MUX

FIFO/

TIMER

AGC

MULT

CART

POLAR

SHIFT

d/dt

x1, x2

x4, x8

FROM

CIC

PATH 0

PATH 2

(4:0)

GAIN

MAG

PHASE

DESTINATION BIT MAP

(BITS 28:18 OF FIR INSTRUCTIONS BIT FIELD)

28 27

25 24 23 22 21 20 19 18

26, 25

22:18

AGC LOOP GAIN SELECT (PATH 01 ONLY)

UPDATE AGC LOOP (PATH 01 ONLY)

PATH 00 - - IMMEDIATE FILTER PROCESSOR FEEDBACK PATH

01 - - FIFO/AGC PATH TO I1 AND Q1

10 - - DIRECT OUT/CASCADE PATH TO I2 AND Q2

11 - - FIFO/AGC PATH TO I2 AND Q2

STROBE OUTPUT SECTION (START SERIAL OUTPUT WITH THIS SAMPLE)

FEED MAG/PHASE BACK TO FILTER PROCESSOR

FILTER PROCESSOR SEQUENCE STEP NUMBER

EXT AGC

GAIN

PATH 1

PATH 3

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