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TLE8250VSJ Datasheet(PDF) 7 Page - Infineon Technologies AG |
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TLE8250VSJ Datasheet(HTML) 7 Page - Infineon Technologies AG |
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7 / 32 page ![]() Data Sheet 7 Rev. 1.0 2016-07-15 TLE8250V High Speed CAN Transceiver Functional Description The TLE8250VSJ is a High-Speed CAN transceiver, operating as an interface between the CAN controller and the physical bus medium. A HS CAN network is a two wire, differential network which allows data transmission rates for CAN FD frames up to 2 MBit/s. Characteristic for HS CAN networks are the two signal states on the HS CAN bus: dominant and recessive (see Figure 3). VCC, VIO and GND are the supply pins for the TLE8250VSJ. The pins CANH and CANL are the interface to the HS CAN bus and operate in both directions, as an input and as an output. RxD and TxD pins are the interface to the CAN controller, the TxD pin is an input pin and the RxD pin is an output pin. The NEN pin is the input pin for the mode selection (see Figure 4). By setting the TxD input pin to logical “low” the transmitter of the TLE8250VSJ drives a dominant signal to the CANH and CANL pins. Setting TxD input to logical “high” turns off the transmitter and the output voltage on CANH and CANL discharges towards the recessive level. The recessive output voltage is provided by the bus biasing (see Figure 1). The output of the transmitter is considered to be dominant, when the voltage difference between CANH and CANL is at least higher than 1.5 V (VDiff = VCANH - VCANL). Parallel to the transmitter the normal-mode receiver monitors the signal on the CANH and CANL pins and indicates it on the RxD output pin. A dominant signal on the CANH and CANL pins sets the RxD output pin to logical “low”, vice versa a recessive signal sets the RxD output to logical “high”. The normal-mode receiver considers a voltage difference (VDiff) between CANH and CANL above 0.9 V as dominant and below 0.5 V as recessive. To be conform with HS CAN features, like the bit to bit arbitration, the signal on the RxD output has to follow the signal on the TxD input within a defined loop delay tLoop ≤ 255 ns. The thresholds of the digital inputs (TxD and NEN) and also the RxD output voltage are adapted to the digital power supply VIO. |
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