AC206-DS05-405-R datasheet(35/70 Pages) BOARDCOM

35 / 70 page

Preliminary Data Sheet

AC206

07/08/02

B roa dcom

Document

AC206-DS05-405-R

PHY Registers

Page 23

PHY REGISTERS

The following registers are defined for each PHY port. The base addresses of PHY 1 to PHY 8 are 0, 1, 2, 3, 4, 5, 6, and 7,

respectively.

PHY CONFIGURATION REGISTER

Table 22: PHY Configuration Register 0

Bit

Name

Definition

Mode

Default

0.15

Reset

1 = PHY reset

This bit is self-clearing.

RW/SC

0.14

Loopback

1 = Loopback mode. Because it internally loops the transmit of

AC206 to its receive, it ignores all the activity on the cable media.

0 = Normal operation.

0.13

Speed Select

1 = 100 Mbps

0 = 10 Mbps. This bit is ignored if auto-negotiation is enabled.

It no longer reflects auto-negotiation results.

0.12

Auto-Neg Enable

1 = Enable auto-negotiate process (overrides 0.13 and 0.8)

0 = Disable auto-negotiate process.

In force mode, speed is selected via bit 0.13.

0.11

Power Down

1 = Power down mode, puts AC206 in low-power stand-by mode,

only react to access transaction.

0 = Normal operation.

0.10

Isolate

1 = Electrical isolation of PHY from MII and cable media.

0 = Normal operation.

0.9

Restart Auto-

Negotiation

1 = Restart auto-negotiation process.

0 = Normal operation.

RW/

0.8

Duplex Mode

1 = Full-duplex.

0 = Half-duplex.

Full-duplex is not supported on this chip. It no longer reflects the

auto-negotiation result.

0.7

Collision Test

1 = Enable collision test, which issues the COL signal in

response to the assertion of TX_EN signal.

0 = Disable COL test.

0.6:0

Reserved

000000

AC206-DS05-405-R Datasheet(PDF) 35 Page - Broadcom Corporation.

AC206-DS05-405-R Datasheet(HTML) 35 Page - Broadcom Corporation.

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70

Datasheet Download

Link URL