ISL6731A, ISL6731B

FN8582 Rev 1.00

Page 2 of 20

February 13, 2015

Pin Configuration

ISL6731A, ISL6731B

(14 LD SOIC)

TOP VIEW

11

12

14

13

4

3

2

1

NC

GND

ISEN

ICOMP

GATE

VCC

VREG

NC

10

5

VIN

SKIP

9

8

6

7

BO

OVP

COMP

FB

Pin Descriptions

PIN #

I/O

SYMBOL

DESCRIPTION

1, 13

-

NC

Not Connected. Must be floating.

2

-

GND

Ground pin. All voltage levels refer to this pin.

3

I

ISEN

Current sense pin. The current through this pin is proportional to the inductor current.

4

I/O

ICOMP

Current error amplifier output pin.

5

I

VIN

Input voltage sense. This pin provides the reference voltage to shape inductor current. Connect this pin to a resistor divider

from the rectified input voltage. The resistor divider ratio is used to adjust the phase lag between input voltage and the

input current. The phase lag is required to compensate the phase lead generated by the EMI filter.

6

I/O

BO

This pin should be decoupled to GND with a minimum 0.1µF ceramic capacitor. The BO pin is a voltage follower, which will

enters shutdown mode and the gate drive is disabled. The BO pin will be disabled when the FB pin drops below the enabling

threshold.

7

I

OVP

Overvoltage protection pin. Connect this pin to a resistor divider from the output. The resistor divider sets the OVP set point.

8

I/O

COMP

Output of the error amplifier. The voltage of the COMP pin sets the input power. During start-up, a small charge current will

slowly ramp up the voltage of the COMP pin.

9

I

FB

Voltage feedback pin. Connect this pin to a resistor divider from the output. The resistor divider sets the output voltage.

10

I/O

SKIP

This pin has dual functions. Connecting this pin to ground disables the light load skip function. An internal 20μA current

sources out of this pin. Connect a resistor from this pin to the ground to set the average power trip point. The converter

11

-

VREG

Output of internal regulator. The voltage having a ±2% tolerance over line, load and operating temperature. Bypass to GND

with a 47nF low ESR capacitor. VREG can source up to 10mA. This pin is not recommended for usage other than bypass.

12

I

VCC

Power supply pin. The VCC pin should be decoupled to GND with a minimum 0.1µF ceramic capacitor.

14

O

GATE

Push-pull gate drive for the external MOSFET. Output voltage is clamped at 12.5V. This pin provides typically 2A sink and

1.5A source capability.