XRT83SL314IB datasheet(65/85 Pages) EXAR

65 / 85 page

XRT83SL314

14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT

PRELIMINARY

REV. P1.0.5

TABLE 32: MICROPROCESSOR REGISTER 0X07H BIT DESCRIPTION

CHANNEL 0-13 (0X07H-0XD7H)

BIT

NAME

FUNCTION

Type

Default

Value

(HW reset)

Reserved

This Register Bit is Not Used.

FLSDET

FIFO LIMIT STATUS DETECT

The FLSDET is used to determine whether the receiver or trans-

mitter FIFO has reached its limit status. If both FIFOs reach their

limit capacity, this bit will be set to "1".

0 = Receive JA

1 = Transmit JA

CLOS5

CLOS4

CLOS3

CLOS2

CLOS1

CLOS0

Cable Loss Indication

This 6-Bit binary word indicates the cable attenuation on the

receiver inputs RTIP/RRING within ±1dB with Bit 5 being the MSB.

TABLE 33: MICROPROCESSOR REGISTER 0X08H BIT DESCRIPTION

CHANNEL 0-13 (0X08H-0XD8H)

BIT

NAME

FUNCTION

Type

Default

Value

(HW reset)

Reserved

This Register Bit is Not Used

1SEG6

1SEG5

1SEG4

1SEG3

1SEG2

1SEG1

1SEG0

Arbitrary Pulse Generation

The transmit output pulse is divided into 8 individual segments.

This register is used to program the first segment which corre-

sponds to the overshoot of the pulse amplitude. There are four

segments for the top portion of the pulse and four segments for the

bottom portion of the pulse. Segment number 5 corresponds to

the undershoot of the pulse. The MSB of each segment is the sign

bit.

Bit 6 = 0 = Negative Direction

Bit 6 = 1 = Positive Direction

R/W

XRT83SL314IB Datasheet(PDF) 65 Page - Exar Corporation

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