ISL8121IRZ datasheet(14/26 Pages) RENESAS

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ISL8121

FN6352 Rev 2.00

Page 14 of 26

October 27, 2009

magnitude, it is important to understand that the PGD

and OVP thresholds will move in proportion to the

moving reference (externally soft-started reference).

ISL8121 POWER-GOOD OPERATION

The open-collector PGD output reports on the quality of

the regulated output voltage. Once the ISL8121 is

enabled and the VMON pin is above its threshold, PGD

goes open circuit when the output enters the power-good

window (see “Electrical Specifications” table on page 6),

and stays open for as long as the output remains within

the specified window. The PGD is immediately pulled low

if the ISL8121 is disabled by removal of bias, toggling of

the EN pin, or upon encountering of an overcurrent

event; PGD is allowed to report the status of the output

as soon as operation is resumed following any of these

events.

The VMON pin is used in external-reference

configurations, where the reference is controlled by a

circuit external to the ISL8121. As such, the ISL8121 has

no way of ‘knowing’ when the external reference has

stabilized to its full value, or is within a certain

percentage of its final value. Thus, the VMON pin’s

functionality can be used to indicate when a desired

threshold has been reached (either by monitoring the

reference itself, or the output voltage controlled by the

ISL8121). By default, when operating in external

reference mode and desiring PGD monitoring as shown in

this datasheet, it is recommended the VMON is set to trip

its threshold when the output voltage (or reference)

reaches 92% of the final set value, choosing the resistor

divider as to achieve a 2% hysteresis.

When operating in internal-reference mode, the value of

the reference is known to the ISL8121, so the VMON pin

function can be bypassed by tying it to VCC potential.

VOLTAGE TRACKING AND SEQUENCING

By making creative use of the reference clamps at the SS

and REFTRK pins, and/or the available external reference

input, as well as the functionality of the EN pin, the

ISL8121 can accommodate the full spectrum of tracking

and sequencing options. Figures 13 and 14 offer some

implementation suggestions for a few typical situations.

Simple ratiometric external voltage tracking, such as that

required by the termination voltage regulator for double

data rate (DDR) memory can be implemented by feeding

a reference voltage equal to 0.5 of the memory core

voltage (VDDQ) to the reference input of the ISL8121, as

shown in Figure 12. The resistor divider at the REFTRK

pin sets the VOUT level. Select a suitable SS capacitor,

such that the SS clamp does not interfere with the

desired ramp-up time or slope of VOUT.

Coincidental tracking using the internal reference results

in a behavior similar to that presented in Figure 13. The

resistor divider at the input of the differential amplifier

sets the output voltage, VOUT, to the desired regulation

level. The same resistor divider used at the REFTRK pin

divides down the voltage to be tracked, effectively

scaling it to the magnitude of the internal reference. As a

result, the output voltage ramps up at the same rate as

the target voltage, its ramp-up leveling off at the

programmed regulation level established by the RS/RP

resistor divider.

VTARGET

VOUT

EXT CIRCUIT

ISL8121

VSEN+

VSEN-

VDIFF

TO VOUT

VREF

E/A

REFTRK

TO VTARGET

VOUT

VTARGET

---------------------------

RP RS

----------------------

FIGURE 12. RATIOMETRIC VOLTAGE TRACKING

VTARGET

VOUT

EXT CIRCUIT

ISL8121

VSEN+

VSEN-

VDIFF

TO VOUT

VREF

E/A

REFTRK

To VTARGET

VREF

VOUT

----------------

RP RS

----------------------

FIGURE 13. COINCIDENTAL VOLTAGE TRACKING

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