EL7584

FN7317 Rev 2.00

Page 13 of 16

February 4, 2005

Two-Stage Negative Charge Pump Circuit

back plane of an LCD display. This plane is capacitively

coupled to the pixel drive voltage which alternately cycles

positive and negative at the line rate for the display. Thus the

amplifier must be capable of sourcing and sinking capacitive

pulses of current, which can occasionally be quite large (a

few 100mA for typical applications).

a voltage, corresponding to the mid-DAC potential, is

generated by a resistive divider and buffered by the

amplifier. The amplifier's stability is designed to be

dominated by the load capacitance, thus for very short

duration pulses (< 1µs) the output capacitor supplies the

current. By virtue of its high transconductance which

progressively increases as more current is drawn, it can

maintain regulation within 5mV as currents up to 50mA are

drawn, while consuming only 1.5mA of quiescent current.

As with any high performance buffer, there are several

design issues that must be considered when using the part.

These are summarized below.

Good Decoupling of Power Supplies

This is essential for this component and 1µF ceramic low

ESR decoupling capacitors are recommended. These

should be placed close to the pins.

Choice of Output Capacitor

A 1µF ceramic capacitor with low ESR (X5R or X7R type) is

recommended for this amplifier. This capacitor determines

the stability of the amplifier. Reducing it will make the

amplifier less stable, and should be avoided. With a 1µF

capacitor, the unity gain bandwidth of the amplifier is close to

-

+

DRVN

FBN

5V-17V

 I

OUT



1





--------------------------------------------





++





1





------------------------------------------------ -



 N2 V

DIODE

1





--------------------------------------------



+









+



1





------------------------------------------------







+



----------



=

-

+

1µF

CERAMIC

LOW ESR

INC

0.1µF