EL7584

FN7317 Rev 2.00

Page 14 of 16

February 4, 2005

500kHz when reasonable currents are being drawn. (For

lower load currents, the gain and hence bandwidth

progressively decreases.) This means the active

transconductance is:

This high transconductance indicates why it is important to

have a low ESR capacitor.

If:

• ESR * 3.14 > 1

then the capacitor will not force the gain to roll off below

unity, and subsequent poles can affect stability. The

recommended capacitor has an ESR of 10m

, but to this

must be added the resistance of the board trace between the

made internally - therefore this should be kept short. Also

must be kept to a minimum. These constraints should be

considered when laying out the PCB.

If the capacitor is increased above 1µF, stability is generally

improved and short pulses of current will cause a smaller

of the amplifier is however degraded as its bandwidth is

decreased. At capacitor values around 10µF, a subtle

interaction with internal DC gain boost circuitry will decrease

the phase margin and may give rise to some overshoot in

the response. The amplifier will remain stable, though.

Response to High Current Spikes

This limit level, which is roughly the same for sourcing and

sinking, is included to maintain reliable operation of the part.

It does not necessarily prevent a large temperature rise if the

current is maintained. (In this case the whole chip may be

shut down by the thermal trip to protect functionality.) If the

display occasionally demands current pulses higher than

this limit, the reservoir capacitor will provide the excess and

the amplifier will top the reservoir capacitor back up once the

pulse has stopped. This will happen on the µs time scale in

practical systems and for pulses 2 or 3 times the current

next line is processed.

Power-Up Sequencing

With the components shown in the application diagram the

on-chip power-up sequencing operates as follows.

When the EN pin is taken to logic 1, the following sequence

is followed by on-chip functions:

1. The boost circuit and negative charge pumps are

capacitor, the external load, and the boost’s current limit

and the current capability of these negative charge

rises.)

of approximately 3.5ms is introduced before the positive

charge pump is then enabled. This delay can be

increased externally by connecting a capacitor between

The enabled states of the on-chip functions become

is triggered. The chip may be reset by forcing EN to logic 0

and allowing sufficient time for the various supplies to

discharge sufficiently before taking EN to 1 again.

Over-Temperature Protection

An internal temperature sensor continuously monitors the

die temperature. In the event that die temperature exceeds

the thermal trip point, the device will shut down and disable

itself. The upper and lower trip points are typically set to

130°C and 90°C respectively.

PCB Layout Guidelines

Careful layout is critical in the successful operation of the

application. The following layout guidelines are

recommended to achieve optimum performance.

to the pins.

2. Place the boost converter diode and inductor close to the

LX pins.

3. Place the boost converter output capacitor close to the

PGND pins.

4. Locate feedback dividers close to their respected

feedback pins to avoid switching noise coupling into the

high impedance node.

5. Place the charge pump feedback resistor network after

the diode and output capacitor node to avoid switching

noise.

6. All low-side feedback resistors should be connected

ground at one point only.

A demo board is available to illustrate the proper layout

implementation.

2

 1F 500kHz





3.14S

=