HIP6006

FN4306 Rev.3.00

Page 7 of 12

April 1, 2005

closed loop transfer function with the highest 0dB crossing

 The equations below relate the compensation network’s

poles, zeros and gain to the components (R1, R2, R3, C1, C2,

and C3) in Figure 8. Use these guidelines for locating the poles

and zeros of the compensation network:

Compensation Break Frequency Equations

1. Pick Gain (R2/R1) for desired converter bandwidth

6. Check Gain against Error Amplifier’s Open-Loop Gain

7. Estimate Phase Margin - Repeat if Necessary

Figure 8 shows an asymptotic plot of the DC-DC converter’s

gain vs frequency. The actual Modulator Gain has a high gain

peak do to the high Q factor of the output filter and is not

shown in Figure 8. Using the above guidelines should give a

Compensation Gain similar to the curve plotted. The open loop

error amplifier gain bounds the compensation gain. Check the

amplifier. The Closed Loop Gain is constructed on the log-log

graph of Figure 8 by adding the Modulator Gain (in dB) to the

Compensation Gain (in dB). This is equivalent to multiplying

the modulator transfer function to the compensation transfer

function and plotting the gain.

The compensation gain uses external impedance networks

loop. A stable control loop has a gain crossing with -

Include worst case component variations when determining

phase margin.

Component Selection Guidelines

Output Capacitor Selection

An output capacitor is required to filter the output and supply

the load transient current. The filtering requirements are a

function of the switching frequency and the ripple current. The

load transient requirements are a function of the slew rate

(di/dt) and the magnitude of the transient load current. These

requirements are generally met with a mix of capacitors and

careful layout.

Modern microprocessors produce transient load rates above

1A/ns. High frequency capacitors initially supply the transient

and slow the current load rate seen by the bulk capacitors. The

bulk filter capacitor values are generally determined by the

ESR (effective series resistance) and voltage rating

requirements rather than actual capacitance requirements.

High frequency decoupling capacitors should be placed as

close to the power pins of the load as physically possible. Be

FIGURE 7. VOLTAGE - MODE BUCK CONVERTER

COMPENSATION DESIGN

OSC

REFERENCE

ESR

ERROR

AMP

PWM

DRIVER

(PARASITIC)

-

REF

R1

R3

R2

C3

C2

C1

COMP

FB

HIP6006

COMPARATOR

DRIVER

DETAILED COMPENSATION COMPONENTS

PHASE

+

-

+

-

+

1

2

 R

 2C1



----------------------------------

=

1

2



R1 R3

+

 C3





------------------------------------------------------

=

1

2

 R2



C1 C2



C1 C2

+

----------------------







-------------------------------------------------------

=

1

2

 R3 C3





----------------------------------

100

80

60

40

20

0

-20

-40

-60

10M

1M

100K

10K

1K

100

10

OPEN LOOP

ERROR AMP GAIN

COMPENSATION

FREQUENCY (Hz)

GAIN

20LOG

MODULATOR

GAIN

20LOG

(R2/R1)

CLOSED LOOP

GAIN

FIGURE 8. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN