ISL6561 datasheet(13/27 Pages) RENESAS

13 / 27 page

ISL6561

FN9098 Rev 6.00

Page 13 of 27

November 10, 2015

INDUCTOR DCR Sensing

An inductor has a distributed direct current winding

resistance (DCR). Consider the inductor DCR as a separate

lumped quantity as shown in Figure 4. The channel current,

IL, flowing through the inductor, also passes through the

DCR. Equation 4 shows the s-domain equivalent voltage,

VL, across the inductor.

A simple R-C network across the inductor extracts the DCR

voltage, as shown in Figure 5.

The voltage on the capacitor, VC, can be shown to be

proportional to the channel current IL(see Equation 5).

If the R-C network components are selected such that the R-

C time constant matches the inductor L/DCR time constant,

then VC is equal to the voltage drop across the DCR.

The capacitor voltage, VC, is replicated across the sense

resistor RISEN. so that the current flowing through the sense

resistor is proportional to the inductor current. Equation 6

shows that the relationship between the channel current and

the sensed current ISEN, is driven by the value of the sense

resistor and the inductor DCR.

Current Sampling

During the forced off-time following a PWM transition low,

the associated channel current sense amplifier reproduces a

signal , ISEN, proportional to the inductor current, IL.

Regardless of the current sense method, ISEN is simply a

scaled version of the inductor current. Coincident with the

falling edge of the PWM signal, the sample and hold circuitry

samples ISEN. This is illustrated in Figure 5. The sample

time, tSAMP, is fixed and equal to 1/3 of the switching period,

tSW. Therefore, the sample current, In, is proportional to the

output current and held for one switching cycle. The sample

current is used for current balance, load-line regulation, and

overcurrent protection.

Channel-Current Balance

The sampled currents In, from each active channel are

summed together and divided by the number of active

channels. The resulting cycle average current, IAVG,

provides a measure of the total load current demand on the

converter during each switching cycle. Channel current

balance is achieved by comparing the sampled current of

each channel to the cycle average current, and making an

appropriate adjustment to each channel pulse width based

on the error. Intersil’s patented current-balance method is

illustrated in Figure 6, with error correction for channel 1

represented. In the figure, the cycle average current

combines with the channel 1 sample, I1, to create an error

signal IER. The filtered error signal modifies the pulse width

commanded by VCOMP to correct any unbalance and force

IER toward zero. The same method for error signal

correction is applied to each active channel.

IL sL DCR







(EQ. 4)

DCR

-------------







DCR IL







sRC 1





---------------------------------------------------------------------

(EQ. 5)

FIGURE 4. DCR SENSING CONFIGURATION

ISEN IL

DCR

RISEN

-------------------

ISEN-

SAMPLE

HOLD

ISL6561 INTERNAL CIRCUIT

VIN

ISEN+

PWM(n)

ISL6561

RISEN

DCR

INDUCTOR

VOUT

COUT

VC(s)

IL s



ISEN

DCR

RISEN

------------------



(EQ. 6)

tSAMP

tSW

----------

3fSW



------------------

(EQ. 7)

FIGURE 5. SAMPLE AND HOLD TIMING

TIME

PWM

SWITCHING PERIOD

ISEN

SAMPLE CURRENT, In

tSAMP

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