80C286 datasheet(11/65 Pages) RENESAS

11 / 65 page

80C286

FN2947 Rev.3.00

Page 11 of 65

January 28, 2008

Memory Organization

Memory is organized as sets of variable-length segments. Each

segment is a linear contiguous sequence of up to 64K (216) 8-bit

bytes. Memory is addressed using a two-component address (a

pointer) that consists of a 16-bit segment selector and a 16-bit off-

set. The segment selector indicates the desired segment in mem-

ory. The offset component indicates the desired byte address

within the segment. (See Figure 3).

All instructions that address operands in memory must specify

the segment and the offset. For speed and compact instruction

encoding, segment selectors are usually stored in the high

speed segment registers. An instruction need specify only the

desired segment register and offset in order to address a mem-

ory operand.

Most instructions need not explicitly specify which segment

chosen according to the rules of Table 3. These rules follow

the way programs are written (see Figure 4) as independent

modules that require areas for code and data, a stack, and

access to external data areas.

Special segment override instruction prefixes allow the implicit

segment register selection rules to be overridden for special

cases. The stack, data and extra segments may coincide for

simple programs. To access operands not residing in one of

the four immediately available segments, a full 32-bit pointer or

a new segment selector must be loaded.

Addressing Modes

The 80C286 provides a total of eight addressing modes for

instructions to specify operands. Two addressing modes are

provided for instructions that operate on register or immediate

operands:

of the 8 or 16-bit general registers.

IMMEDIATE OPERAND MODE: The operand is included in

the instruction.

Six modes are provided to specify the location of an operand in a

memory segment. A memory operand address consists of two

16-bit components: segment selector and offset. The segment

selector is supplied by a segment register either implicitly chosen

by the addressing mode or explicitly chosen by a segment over-

ride prefix. The offset is calculated by summing any combination

of the following three address elements:

the displacement (an 8 or 16-bit immediate value contained in

the instruction)

the base (contents of either the BX or BP base registers)

the index (contents of either the SI or Dl index registers)

Any carry out from the 16-bit addition is ignored. Eight-bit dis-

placements are sign extended to 16-bit values.

TABLE 3. SEGMENT REGISTER SELECTION RULES

MEMORY

REFERENCE

NEEDED

SEGMENT

USED

IMPLICIT SEGMENT

SELECTION RULE

Instructions

Code (CS) Automatic with instruction prefetch

Stack

Stack (SS) All stack pushes and pops. Any

memory reference which uses BP

as a base register.

Local Data

Data (DS)

All data references except when

relative to stack or string destination

External

(Global) Data

Extra (ES) Alternate data segment and

destination of string operation

POINTER

OFFSET

SEGMENT

16 15

OPERAND

SELECTED

SEGMENT

MEMORY

SELECTED

FIGURE 3. TWO COMPONENT ADDRESS

CODE

DATA

CODE

DATA

MEMORY

CPU

CODE

DATA

STACK

EXTRA

SEGMENT

REGISTERS

MODULE A

MODULE B

PROCESS

STACK

PROCESS

DATA

BLOCK 1

PROCESS

DATA

BLOCK 2

FIGURE 4. SEGMENTED MEMORY HELPS STRUCTURE

SOFTWARE

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