80C286 datasheet(13/65 Pages) RENESAS

13 / 65 page

80C286

FN2947 Rev.3.00

Page 13 of 65

January 28, 2008

I/O Space

The I/O space consists of 64K 8-bit ports, 32K 16-bit ports, or a

combination of the two. I/O instructions address the I/O space

with either an 8-bit port address, specified in the instruction, or a

16-bit port address in the DX register. 8-bit port addresses are

zero extended such that A15-A8 are LOW. I/O port addresses

00F8(H) through 00FF(H) are reserved.

Interrupts

An interrupt transfers execution to a new program location.

The old program address (CS:lP) and machine state (Flags)

are saved on the stack to allow resumption of the interrupted

program. Interrupts fall into three classes: hardware initiated,

INT instructions, and instruction exceptions. Hardware initiated

interrupts occur in response to an external input and are classi-

fied as non-maskable or maskable. Programs may cause an

interrupt with an INT instruction. Instruction exceptions occur

when an unusual condition which prevents further instruction

processing is detected while attempting to execute an instruc-

tion. The return address from an exception will always point to

the instruction causing the exception and include any leading

instruction prefixes.

A table containing up to 256 pointers defines the proper inter-

rupt service routine for each interrupt. Interrupts 0-31, some of

which are used for instruction exceptions, are reserved. For

each interrupt, an 8-bit vector must be supplied to the 80C286

which identifies the appropriate table entry. Exceptions supply

the interrupt vector internally. INT instructions contain or imply

the vector and allow access to all 256 interrupts. Maskable

hardware initiated interrupts supply the 8-bit vector to the CPU

during an interrupt acknowledge bus sequence. Nonmaskable

hardware interrupts use a predefined internally supplied vec-

tor.

Maskable Interrupt (INTR)

The 80C286 provides a maskable hardware interrupt request

pin, INTR. Software enables this input by setting the interrupt

flag bit (IF) in the flag word. All 224 user-defined interrupt

sources can share this input, yet they can retain separate inter-

rupt handlers. An 8-bit vector read by the CPU during the inter-

rupt acknowledge sequence (discussed in System Interface

section) identifies the source of the interrupt.

The processor automatically disables further maskable inter-

rupts internally by resetting the IF as part of the response to an

interrupt or exception. The saved flag word will reflect the

enable status of the processor prior to the interrupt. Until the

flag word is restored to the flag register, the interrupt flag will

be zero unless specifically set. The interrupt return instruction

includes restoring the flag word, thereby restoring the original

status of IF.

Non-Maskable Interrupt Request (NMI)

A non-maskable interrupt input (NMI) is also provided. NMI has

higher priority than INTR. A typical use of NMI would be to acti-

vate a power failure routine. The activation of this input causes

an interrupt with an internally supplied vector value of 2. No

external interrupt acknowledge sequence is performed.

While executing the NMI servicing procedure, the 80C286 will

service neither further NMI requests, INTR requests, nor the

processor extension segment overrun interrupt until an inter-

rupt return (lRET) instruction is executed or the CPU is reset. If

NMI occurs while currently servicing an NMI, its presence will

be saved for servicing after executing the first IRET instruction.

IF is cleared at the beginning of an NMI interrupt to inhibit INTR

interrupts.

TABLE 4. INTERRUPT VECTOR ASSIGNMENTS

FUNCTION

INTERRUPT

NUMBER

INSTRUCTIONS

DOES RETURN ADDRESS

POINT TO INSTRUCTION

CAUSING EXCEPTION?

Divide Error Exception

DlV, lDlV

Yes

Single Step Interrupt

All

NMI Interrupt

INT 2 or NMI Pin

Breakpoint Interrupt

INT 3

INTO Detected Overflow Exception

INTO

BOUND Range Exceeded Exception

BOUND

Yes

Invalid Opcode Exception

Any Undefined Opcode

Yes

Processor Extension Not Available Exception

ESC or WAIT

Yes

Reserved - Do Not Use

8 - 15

Processor Extension Error Interrupt

ESC or WAIT

Reserved

17 - 31

User Defined

32 - 255

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