ADL5315

Data Sheet

Rev. A | Page 10 of 17

The VSET control is intended primarily to provide a dc bias

voltage for the mirror input, but it is also well behaved in the

independent of input current because the mirror is capable of

sourcing large currents to pull up the INPT pin. The fall time,

available to discharge the input compensation capacitor and

other parasitics (see Figure 11). The mirror output current can

fully settled.

NOISE PERFORMANCE

The noise performance for the ADL5315, defined as the rms

noise current as a fraction of the output dc current, generally

improves with increasing signal current. This partially results

from the relationship between the quiescent collector current

and the shot noise in the bipolar transistors. At lower signal

current levels, the noise contribution from the JFET amplifier

and other voltage noise sources appearing at INPT contribute

significantly to the current noise. Filtering noise at VSET,

whether provided by SREF or generated externally, as well as

selecting optimal external compensation components on INPT,

minimizes the amount of current noise at IOUT generated by

the voltage noise at INPT.

MIRROR RESPONSE TIME

function of input current, with small-signal bandwidth increasing

external compensating capacitor on INPT strongly affects the

in the Bias Control Interface section), although the value must

be chosen to maintain stability and prevent noise peaking.

INPUT CURRENT LIMITING

The ADL5315 provides a resistor-programmable input current

limit with a fixed maximum of 16 mA for the RLIM pin tied to

VPOS. The fixed maximum provides input short-circuit protection

to ground. The current limit is defined as the current that forces

current limit according to

kΩ

3

V

48

+

=

LIM

LIM

R

I

1 mA (down to approximately 250 µA) with some degradation

in accuracy. See Figure 14 for more performance detail.