ZL8802 datasheet(86/88 Pages) RENESAS

86 / 88 page

ZL8800

FN7558 Rev.6.00

Page 86 of 88

Nov 8, 2017

Firmware Revision History

FIRMWARE REVISION CODE

CHANGE DESCRIPTION

NOTE

1.06

Fix to start-up routine to improve SA pin read performance at cold

temperatures.

Improved fault retry performance.

Improved DDC compatibility with previous generations of Intersil

controllers and modules.

Addition of the LEGACY_FAULT_GROUP command to allow for fault

spreading over Intersil’s DDC bus with previous generation of

controllers and modules.

Defaults for IOUT_XXX and TOFF_FALL are fixed values; they are no

longer dependent on other command values.

Some command defaults may differ from 1.04 values by one bit.

TOFF_DELAY settings less than 0.5ms will set the device to

immediate off shutdown behavior.

INTERLEAVE default automatically phase spread in 2 channel

mode.

DDC_CONFIG default automatically sets group number.

Recommended for new designs

1.04

Initial release

Not recommended for new designs

Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted.

Please visit our website to make sure you have the latest revision.

DATE

REVISION

CHANGE

Nov 8, 2017

FN7558.6

Added an explanation of the EN0 and EN1 timing restrictions to “Enable Pin Operation and Timing” on

page 15.

Updated to the current Renesas format.

Aug 10, 2017

FN7558.5

In the Features section, updated the voltage range to “4.5V to 5.5V or 6.5V to 14V”

Updated application diagrams to show use of DRMOS devices.

Added a two phase schematic diagram with DrMOS.

Pin Description section

For the SCL and SDA pins, added “Requires a pull-up resistor to a 2.5V to 5.5V (recommend VR5, do not use

V25) source. Pull-up supply must be from an “always on” source or VR5.”

For the SALRT pin, added “Requires a pull-up resistor to a 2.5V to 5.5V (recommend VR5, do not use V25)

source. Leave floating if not used.”

For the SGND pin, added “All pin-strap resistors should be connected to SGND. SGND must be connected to

DGND and PGND using a single point connection.”

For the SA pin, added “Connect resistor to SGND.”

For VSET0, added “Default VOUT max is 115% of VOUT setting, but this can be overridden through the PMBus

interface with the VOUT_MAX command. Connect resistor to SGND.”

For VSET1, added “Default VOUT max is 115% of VOUT setting, but this can be overridden through the PMBus

interface with the VOUT_MAX command. Connect resistor to SGND. NOT USED IN 2-PHASE MODE. Leave

floating in 2-phase mode.”

For XTEMP0P, XTEMP0N, VTRKP, and VTRKN, added “If not used connect to SGND.”

For VDRV, VR6, and VR5, added “10µF recommended.”

For VSEN1N, added “in 2-channel or 2-phase mode.”

For VSEN1P, added “in 2-channel or 2-phase mode.”

In the Ordering Information table, added “Recommended for new designs” column.

For 4Bh IOUT_UC_FAULT_LIMIT, changed the default setting to “-20A”.

For 65h TOFF_FALL, changed the default setting to “5ms”.

For E7h IOUT_AVG_OC_FAULT_LIMIT, changed the default setting to “16A”.

For E8h IOUT_AVG_UC_FAULT_LIMIT, changed the default setting to “-16A”.

For 80h STATUS_MFR_SPECIFIC, reworded VMON_UV_WARNING and VMON_OV_WARNING for clarity.

In the Firmware Revision History, added some previously undocumented firmware changes to the 1.06

revision.

Added a recommendation for 10uF bypass capacitor on VR5, VR6, and VDRV.

Added a recommendation to pull-up DDC to VR5.

Corrected several PMBus command descriptions to show correct default value and Global or Paged

behavior.

ZL8802 Datasheet(PDF) 86 Page - Renesas Technology Corp

ZL8802 Datasheet(HTML) 86 Page - Renesas Technology Corp

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