FT29F010B datasheet(2/30 Pages) FORCE

2 / 30 page

GENERAL DESCRIPTION

The

FT29F010B is a 1 Mbit, 5.0 Volt-only Flash

memory organi

sed as 131,072 bytes. The FT29F010B

is offered in 32-pin

various packages.

The byte-wide data appears on DQ0-DQ7. The de-

vice is designed to be programmed in-system with the

standard system 5.0 Volt VCC supply. A 12.0 volt VPP is not

required for program or erase operations. The device can

also be programmed or erased in standard EPROM

programmers.

This device is manufactured using 0.32 µm pro

cess

technology

The standard device offers access times

90, and 120 ns, allowing high-speed microprocessors

to operate without wait states. To eliminate bus conten-

tion the device has separate chip enable (CE#), write

enable (WE#) and output enable (OE#) controls.

The device requires only a single 5.0 volt power sup-

ply for both read and write functions. Internally

generated and regulated voltages are provided for the

program and erase operations.

The device is entirely command set compatible with the

JEDEC single-power-supply Flash standard. Com-

mands are written to the command register using

standard microprocessor write timings. Register con-

tents serve as input to an internal state machine that

controls the erase and programming circuitry. Write

cycles also internally latch addresses and data needed

for the programming and erase operations. Reading

data out of the device is similar to reading from other

Flash or EPROM devices.

Device programming occurs by executing the program

command sequence. This invokes the Embedded Pro-

gr a m a l go r i t h m — an in te r na l a l go r i t hm t h at

automatically times the program pulse widths and

verifies proper cell margin.

Device erasure occurs by executing the erase com-

mand sequence. This invokes the Embedded Erase

algorithm—an internal algorithm that automatically

preprograms the array (if it is not already programmed)

before executing the erase operation. During erase, the

device automatically times the erase pulse widths and

verifies proper cell margin.

The host system can detect whether a program or

erase operation is complete by reading the DQ7 (Data#

Polling) and DQ6 (toggle) status bits. After a program

or erase cycle has been completed, the device is ready

to read array data or accept another command.

The sector erase architecture allows memory sectors

to be erased and reprogrammed without affecting the

data contents of other sectors. The device is erased

when shipped from the factory.

The hardware data protection measures include a

low VCC detector automatically inhibits write operations

during power transitions. The hardware sector protec-

tion feature disables both program and erase operations

in any combination of the sectors of memory, and is im-

plemented using standard EPROM programmers.

The system can place the device into the standby mode.

Power consumption is greatly reduced in this mode.

The device electrically erases all bits

within a sector simultaneously via Fowler-Nordheim

tunneling. The bytes are programmed one byte at a

time using the EPROM programming mechanism of hot

electron injection.

Rev 2

2/30

2014

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