LTC6957-4 datasheet(23/38 Pages) AD

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Figure 6. CMOS Input

Figure 6 shows a suggested CMOS to LTC6957 interface.

The transmission line shown is the PCB trace and the

component values are for a characteristic impedance of

50Ω, though they could be scaled up or down for other

values of Z0. The R1/R2 divider at the CMOS output cuts

the Thevenin voltage in half when the ZOUT of the driver is

included. More importantly, it drives the transmission line

with a Thevenin driving resistance of 50Ω, matching the

Z0 of the line. On the other end of the line, a 50Ω load is

presented, minimizing reflections. This results in a second

2:1 attenuation in voltage, so the LTC6957 input will be

approximately 800mVP-P with 3V CMOS; 1.25VP-P with 5V

and 600mVP-P with 2.5V. All of these levels are less than

the maximum input swing of 2VP-P yet with clean edges

and fast slew rates should be able to realize the full phase

noise performance of the LTC6957.

phase noise spectrum related to the other signals pro-

cessed in the driver.

Input Resistors

The LTC6957 input resistors, seen in Figure 1, are present

at all times, including during shutdown. Although they

constitute a large portion of the shutdown current, this

behavior prevents the shutdown and wake-up cycling of

the LTC6957 from “kicking back” into prior stages, which

could create large transients that could take a while to

settle. Particularly in the common case of AC-coupling

where the coupling cap charge is preserved.

Input Filtering

The LTC6957 includes input filtering with three narrow-

band settings in addition to the full bandwidth limitation

of the circuit design.

Table 1

FILTA

FILTB

BANDWIDTH

Low

1200MHz (Full Bandwidth)

High

Low

500MHz (–3dB)

Low

High

160MHz (–3dB)

High

50MHz (–3dB)

For slow slewing signals (i.e., <100MHz sine wave sig-

nals) substantially lower phase noise can be achieved by

using this feature. Bandwidth limiting is useful because it

limits the impact of all of the spectral energy that will alias

down to (on top of) the fundamental frequency.

The best filter setting to use for a given application will

depend on the clock frequency, amplitude, and waveform

shape, with the single biggest determinant being the slew

rate at the input of the LTC6957. Any amplifier noise will

add phase noise inversely proportional to its input slew

rate, just from the dV/dt changing voltage noise to time

base noise. But a fast slew rate may not be possible with

other design constraints, such as the use of sine waves

for EMI/RFI reasons, signal losses, etc. A limiting ampli-

fier such as the LTC6957 should have enough bandwidth

to preserve the slew rate of the input. But any additional

bandwidth will provide no improvement in phase noise

due to slew rate preservation, while incurring a phase

noise penalty from noise aliasing.

APPLICATIONS INFORMATION

6957 F06

–

LTC6957

75Ω

CMOS

ROUT ≈ 25

100Ω

50Ω

Z0 = 50Ω

The various capacitors are for AC-coupling and should

have Z << 50Ω at the operating frequency. The capacitors

allow the LTC6957 to set its own DC input bias level, and

reduce the DC current drain, which at 12.4mA (for the

case of a driver powered from 3.3V) is significant. This

current drain can be reduced (with some potential for a

noise penalty) by increasing the attenuation at the R1/

R2 network, taking care to keep the Thevenin impedance

equal to the Z0 of the trace.

When using CMOS logic, it is important to consider how

all of the output drivers, in the same IC, are being used.

For best performance, the entire IC should be devoted to

driving the LTC6957, or if other gates in the same pack-

age must be put to use, they should only carry the same

timing signal (such as for fan-out) or be multiplexed in

time so that only one timing signal is being processed at

a time, such as for multiplexing selective shutdowns of

different segments of a system. Otherwise performance

is likely to suffer with spurs or other interference in the

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