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TAS5805MPWPR Datasheet(PDF) 48 Page - Texas Instruments

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Part # TAS5805MPWPR
Description  23-W, Inductor-Less, Digital Input, Stereo, Closed-Loop Class-D Audio Amplifier with Enhanced Processing and Low Idle Power Dissipation
PDF  86 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

TAS5805MPWPR Datasheet(HTML) 48 Page - Texas Instruments

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TAS5805M
SLASEH5A – MAY 2018 – REVISED JULY 2018
www.ti.com
Product Folder Links: TAS5805M
Submit Documentation Feedback
Copyright © 2018, Texas Instruments Incorporated
9.6.1.17 DIG_VOL_CTRL3 Register (Offset = 4Fh) [reset = 0x30]
DIG_VOL_CTRL3 is shown in Figure 84 and described in Table 23.
Return to Summary Table.
Figure 84. DIG_VOL_CTRL3 Register
7
6
5
4
3
2
1
0
FAST_RAMP_DOWN_SPEED
FAST_RAMP_DOWN_STEP
RESERVED
R/W
R/W
R/W
Table 23. DIG_VOL_CTRL3 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-6
FAST_RAMP_DOWN_SP
EED
R/W
00
Digital Volume Emergency Ramp Down Frequency
These bits control the frequency of the digital volume updates when
the volume is ramping down due to clock error or power outage,
which usually needs faster ramp down compared to normal soft
mute.
00: Update every 1 FS period
01: Update every 2 FS periods
10: Update every 4 FS periods
11: Directly set the volume to zero (Instant mute)
5-4
FAST_RAMP_DOWN_ST
EP
R/W
11
Digital Volume Emergency Ramp Down Step
These bits control the step of the digital volume updates when the
volume is ramping down due to clock error or power outage, which
usually needs faster ramp down compared to normal soft mute.
00: Decrement by 4 dB for each update
01: Decrement by 2 dB for each update
10: Decrement by 1 dB for each update
11: Decrement by 0.5 dB for each update
3-0
RESERVED
R/W
0000
This bit is reserved
9.6.1.18 AUTO_MUTE_CTRL Register (Offset = 50h) [reset = 0x07]
AUTO_MUTE_CTRL is shown in Figure 85 and described in Table 24.
Return to Summary Table.
Figure 85. AUTO_MUTE_CTRL Register
7
6
5
4
3
2
1
0
RESERVED
REG_AUTO_MUTE_CTRL
R/W
R/W
Table 24. AUTO_MUTE_CTRL Register Field Descriptions
Bit
Field
Type
Reset
Description
7-3
RESERVED
R/W
00000
This bit is reserved
2-0
REG_AUTO_MUTE_CTR
L
R/W
111
bit0:
0: Disable left channel auto mute
1: Enable left channel auto mute
bit1:
0: Disable right channel auto mute
1: Enable right channel auto mute
bit2:
0: Auto mute left channel and right channel independently.
1: Auto mute left and right channels only when both channels are
about to be auto muted.



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