TVP3025 datasheet(13/99 Pages) TI

13 / 99 page

1–7

1.5

Terminal Functions (Continued)

TERMINAL

I/O

DESCRIPTION

NAME

NO.

I/O

DESCRIPTION

P0 – P63

3 – 16, 19 – 38,

110 – 116,

127 – 135,

138 – 141,

149 – 158

(TTL

compatible)

Pixel input port. The port can be used in various modes as shown in

Table 2–8 (TVP3020 mode) or Table 2–15 (BT485 mode). All the

unused terminals need to be tied to GND.

RCLK

124

(TTL

compatible)

Reference clock output. RCLK is essentially the same as the SCLK

output but not gated off during blank. It can be used for pixel-port timing

reference or other system synchronization and is programmed through

the output-clock-selection register in TVP3020 mode. In BT485 mode

RCLK is similar to the BT485 SCLK, with the divide ratio (and hence the

multiplex ratio) being automatically set when command register 1 is

programmed for the desired operating mode.

REF

Voltage reference for DACs. An internal voltage reference of nominally

1.235 V is provided, which requires an external 0.1-

µF ceramic

capacitor between REF and analog GND. However, the internal

reference voltage can be overdriven by an externally supplied

reference voltage. Typical connection is shown in Appendix A.

RESET

Chip reset. All the registers default to the VGA mode after reset.

(TTL

compatible)

Read strobe input. A logic 0 on this terminal initiates a read from the

the low-going edge of RD (see Figure 3–1).

RS0 – RS4

41, 42, 55 – 57

(TTL

compatible)

be inverted internally using the MODE2 input. RS3 has an internal pull

down resistor so these terminals may be left unconnected if only RS0 –2

are used for the TVP3020-only operation.

SCLK

126

(TTL

compatible)

Shift clock output. SCLK is selected as a division of the dot clock input.

The output signals are gated off during blank, although SCLK is still

used internally to synchronize with the activation of BLANK.

SENSE

(TTL

compatible)

Test mode DAC comparator output signal. This terminal is low if one or

more of the DAC output analog levels is above the internal comparator

reference of 350 mV

±50 mV.

SFLAG

105

(TTL

compatible)

Split shift register transfer flag. The TVP3025 detects a low-to-high

transition on this terminal during a blank sequence and immediately

generates an SCLK pulse. This early SCLK pulse replaces the first

SCLK pulse in the normal sequence.

SYSBL

101

(TTL

compatible)

System blank input. SYSBL is active (low).

SYSHS,

SYSVS

99, 100

(TTL

compatible)

System horizontal and vertical sync inputs. These signals are used to

generate the sync level on the green current output. They are active

(low) inputs, but the HSYNCOUT and VSYNCOUT output polarities can

be programmed through the general-control register.

VCLK

125

(TTL

compatible)

Video clock output. VCLK is the user-programmable output for

synchronization to a graphics processor. It can be used to latch SYSBL,

SYSHS, SYSVS inputs (depending on miscellaneous-control register

bit 6).

NOTE: All unused inputs should be tied to a logic level and not be allowed to float.

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