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D5V0FS4U10LP Datasheet(PDF) 2 Page - Diodes Incorporated |
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D5V0FS4U10LP Datasheet(HTML) 2 Page - Diodes Incorporated |
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2 / 5 page ![]() D5V0FS4U10LP Document number: DS39520 Rev. 1 – 2 2 of 5 www.diodes.com September 2017 © Diodes Incorporated D5V0FS4U10LP Maximum Ratings (@TA = +25°C, unless otherwise specified.) Characteristic Symbol Value Unit Conditions Peak Pulse Current, per IEC 61000-4-5 IPP 3.5 A I/O to VSS, 8/20µs Peak Pulse Power, per IEC 61000-4-5 PPP 20 W I/O to VSS, 8/20µs ESD Protection – Contact Discharge, per IEC 61000-4-2 VESD_CONTACT ±8 kV I/O to VSS ESD Protection – Air Discharge, per IEC 61000-4-2 VESD_AIR ±8 kV I/O to VSS Thermal Characteristics Characteristic Symbol Value Unit Power Dissipation Typical (Note 5) PD 350 mW Thermal Resistance, Junction to Ambient Typical (Note 5) RJA 360 °C/W Operating and Storage Temperature Range TJ,TSTG -55 to +150 °C Electrical Characteristics (@TA = +25°C, unless otherwise specified.) Characteristic Symbol Min Typ Max Unit Test Conditions Reverse Working Voltage VRWM — — 5 V — Reverse Current IR — — 1 μA VR = 5V, I/O to VSS Reverse Breakdown Voltage VBR 5.5 7.0 — V IR = 1mA, I/O to VSS Forward Clamping Voltage VF -1.0 -0.85 — V IF = -15mA, I/O to VSS Holding Reverse Voltage VHOLD — 1.19 — V I/O to VSS Holding Reverse Current IHOLD — 90 — mA I/O to VSS Reverse Clamping Voltage (Note 6) VC — 3 — V IPP = 3A, I/O to VSS, 8/20µs Clamping Voltage (Note 7) VC — 6 — V TLP, 16A, tp = 100ns, I/O to VSS Clamping Voltage (Note 7) VC — 4.5 — V TLP, -16A, tp = 100ns, I/O to VSS Dynamic Reverse Resistance RDIF-R — 0.25 — Ω TLP, 10A, tp = 100ns, I/O to VSS Dynamic Forward Resistance RDIF-F — 0.2 — Ω TLP, 10A, tp = 100ns, VSS to I/O Channel Input Capacitance CI/O — 0.45 55 — pF VI/O = 0V, VSS = 0V, f = 1MHz Notes: 5. Device mounted on FR-4 PCB pad layout (2oz copper) as shown on Diodes Incorporated’s suggested pad layout, which can be found on our website at http://www.diodes.com/package-outlines.html. 6. Clamping voltage value is based on an 8x20µs peak pulse current (IPP) waveform. 7. Clamping voltage value is based on an TLP model. TLP conditions: Z0=50Ω, tp = 100ns, averaging window; t1=70ns to t2=90ns. |
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