PCT2202

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© NXP Semiconductors N.V. 2015. All rights reserved.

Product data sheet

Rev. 1.1 — 14 August 2015

12 of 30

NXP Semiconductors

PCT2202

8.

Bus overview

lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be

connected to a positive supply via a pull-up resistor when connected to the output stages

of a device. Data transfer may be initiated only when the bus is not busy.

The device that initiates the transfer is called a ‘master’, and the devices controlled by the

master are ‘slaves’. The bus must be controlled by a master device that generates the

serial clock (SCL), controls the bus access, and generates the START and STOP

conditions.

To address a specific device, a START condition is initiated, indicated by pulling the

data line (SDA) from a HIGH to LOW logic level while SCL is HIGH. All slaves on the bus

shift in the slave address byte on the rising edge of the clock, with the last bit indicating

whether a read or write operation is intended. During the ninth clock pulse, the slave being

addressed responds to the master by generating an Acknowledge and pulling SDA LOW.

Data transfer is then initiated and sent over eight clock pulses followed by an

Acknowledge bit. During data transfer SDA must remain stable while SCL is HIGH,

because any change in SDA while SCL is HIGH will be interpreted as a START or STOP

signal.

Once all data have been transferred, the master generates a STOP condition indicated by

pulling SDA from LOW to HIGH, while SCL is HIGH.

8.1 Serial interface

the bus are made via the open-drain I/O lines SDA and SCL. The SDA and SCL pins

feature integrated spike suppression filters and Schmitt triggers to minimize the effects of

input spikes and bus noise. The PCT2202 supports the transmission protocol for Standard

mode, Fast mode, Fast-mode Plus (1 kHz to 1 MHz) and High-speed mode (1 kHz to

3.4 MHz). All data bytes are transmitted MSByte first.

Table 13.

Extended mode 13-bit configuration shown in parentheses.

Byte

D7

D6

D5

D4

D3

D2

D1

D0

1H11

(H12)

H10

(H11)

H9

(H10)

H8

(H9)

H7

(H8)

H6

(H7)

H5

(H6)

H4

(H5)

2H3

(H4)

H2

(H3)

H1

(H2)

H0

(H1)

0

(H0)

0

(0)

0

(0)

0

(0)

Table 14.

Extended mode 13-bit configuration shown in parentheses.

Byte

D7

D6

D5

D4

D3

D2

D1

D0

1L11

(L12)

L10

(L11)

L9

(L10)

L8

(L9)

L7

(L8)

L6

(L7)

L5

(L6)

L4

(L5)

2L3

(L4)

L2

(L3)

L1

(L2)

L0

(L1)

0

(L0)

0

(0)

0

(0)

0

(0)