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S71PL129JC0BAI9P2 Datasheet(PDF) 79 Page - SPANSION |
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S71PL129JC0BAI9P2 Datasheet(HTML) 79 Page - SPANSION |
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79 / 149 page  Ocotober 16, 2004 pSRAM_Type06_14_A1 pSRAM Type 6 79 Advance Informatio n pSRAM Type 6 2M Word by 16-bit Cmos Pseudo Static RAM (32M Density) 4M Word by 16-bit Cmos Pseudo Static RAM (64M Density) Features Single power supply voltage of 2.6 to 3.3 V Direct TTL compatibility for all inputs and outputs Deep power-down mode: Memory cell data invalid Page operation mode: — Page read operation by 8 words Logic compatible with SRAM R/W pin Standby current — Standby = 70 µA (32M) — Standby = 100 µA (64M) — Deep power-down Standby = 5 µA Access Times Pin Description 32M 64M Access Time 70 ns CE1# Access Time 70 ns OE# Access Time 25 ns Page Access Time 30 ns Pin Name Description A0 to A21 Address Inputs A0 to A2 Page Address Inputs I/O1 to I/O16 Data Inputs/Outputs CE1# Chip Enable Input CE2 Chip select Input WE# Write Enable Input OE# Output Enable Input LB#,UB# Data Byte Control Inputs VDD Power Supply GND Ground NC Not Connection |
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