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AD9144BCPZ Datasheet(PDF) 4 Page - Analog Devices |
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AD9144BCPZ Datasheet(HTML) 4 Page - Analog Devices |
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4 / 125 page  AD9144 Data Sheet Rev. B | Page 4 of 125 FUNCTIONAL BLOCK DIAGRAM SYNCOUT0– SYNCOUT0+ PROTECT_OUT1 PROTECT_OUT0 DAC PLL SERDES PLL POWER-ON RESET SERIAL I/O PORT CONFIG REGISTERS PLL_CTRL DACCLK PLL_LOCK SYNCHRONIZATION LOGIC DAC ALIGN DETECT HB1 SERDIN7± V TT SERDIN0± SYNCOUT1+ SYNCOUT1– REF AND BIAS I120 SYSREF+ SYSREF– HB3 HB2 DACCLK OUT3+ OUT3– f DAC ÷4, ÷8 NCO COMPLEX MODULATION PHASE ADJUST Q-GAIN I-GAIN SYSREF Rx CLK+ CLK– MODE CONTROL DACCLK CLK Rx HB3 HB2 HB1 Q-OFFSET I-OFFSET HB1 HB3 HB2 MODE CONTROL HB3 HB2 HB1 FSC FSC OUT2+ OUT2– DACCLK OUT1+ OUT1– f DAC ÷4, ÷8 NCO COMPLEX MODULATION PHASE ADJUST Q-GAIN I-GAIN Q-OFFSET I-OFFSET FSC FSC OUT0+ OUT0– CLOCK DISTRIBUTION AND CONTROL LOGIC Figure 2. |
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