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AD9144BCPZ Datasheet(PDF) 39 Page - Analog Devices

Part # AD9144BCPZ
Description  Digital-to-Analog Converter
PDF  125 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD9144BCPZ Datasheet(HTML) 39 Page - Analog Devices

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Data Sheet
AD9144
Rev. B | Page 39 of 125
SERDIN0±/PHYSICAL LANE 0
SERDIN1±/PHYSICAL LANE 1
SERDIN2±/PHYSICAL LANE 2
SERDIN3±/PHYSICAL LANE 3
SERDIN4±/PHYSICAL LANE 4
SERDIN5±/PHYSICAL LANE 5
SERDIN6±/PHYSICAL LANE 6
SERDIN7±/PHYSICAL LANE 7
LOGICAL LANE 0/LINK 0 LANE 0
LOGICAL LANE 1/LINK 0 LANE 1
LOGICAL LANE 2/LINK 0 LANE 2
LOGICAL LANE 3/LINK 0 LANE 3
LOGICAL LANE 4/LINK 0 LANE 4
LOGICAL LANE 5/LINK 0 LANE 5
LOGICAL LANE 6/LINK 0 LANE 6
LOGICAL LANE 7/LINK 0 LANE 7
PHYSICAL LANES
LOGICAL LANES
DAC0
DAC1
DAC2
DAC3
QUAD-BYTE
DEFRAMER
(QBD0)
SERDIN0±/PHYSICAL LANE 0
SERDIN1±/PHYSICAL LANE 1
SERDIN2±/PHYSICAL LANE 2
SERDIN3±/PHYSICAL LANE 3
SERDIN4±/PHYSICAL LANE 4
SERDIN5±/PHYSICAL LANE 5
SERDIN6±/PHYSICAL LANE 6
SERDIN7±/PHYSICAL LANE 7
LOGICAL LANE 0/LINK 0 LANE 0
LOGICAL LANE 1/LINK 0 LANE 1
LOGICAL LANE 2/LINK 0 LANE 2
LOGICAL LANE 3/LINK 0 LANE 3
LOGICAL LANE 4/LINK 1 LANE 0
LOGICAL LANE 5/LINK 1 LANE 1
LOGICAL LANE 6/LINK 1 LANE 2
LOGICAL LANE 7/LINK 1 LANE 3
PHYSICAL LANES
LOGICAL LANES
DAC0
DAC1
DAC2
DAC3
PHYSICAL
LAYER (PHY)
CROSSBAR
LOGICAL
LAYER
QBD
DAC CORE
CROSSBAR
REGISTER
0x308
TO
REGISTER
0x30B
CROSSBAR
REGISTER
0x308
TO
REGISTER
0x30B
QUAD-BYTE
DEFRAMER 0
(QBD0)
QUAD-BYTE
DEFRAMER 1
(QBD1)
Figure 42. Link Mode Functional Diagram
LANE 0 DESERIALIZED
AND DESCRAMBLED DATA
LANE 0 DATA CLOCK
SERDIN0
FIFO
SERDIN7
FIFO
CROSS
BAR
SWITCH
LANE 7 DESERIALIZED
AND DESCRAMBLED DATA
LANE 7 DATA CLOCK
PCLK
DATA LINK LAYER
SPI CONTROL
SYSREF
SYNCOUTx±
SYSTEM CLOCK
PHASE DETECT
LANE0 OCTETS
LANE7 OCTETS
QUAD-BYTE
DEFRAMER
QBD
Figure 43. Data Link Layer Block Diagram



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