24AA164

DS21100F-page 6

© 1999 Microchip Technology Inc.

FIGURE 4-1:

BYTE WRITE

FIGURE 4-2:

PAGE WRITE

S

T

O

P

SDA LINE

P

DATA

S

T

A

R

T

CONTROL

BYTE

S

WORD

ADDRESS

BUS ACTIVITY:

MASTER

BUS ACTIVITY:

A

C

K

A

C

K

A

C

K

1 A2

B0

A1 A0 B2 B1

S

T

O

P

SDA LINE

P

DATA n

S

T

A

R

T

CONTROL

BYTE

WORD

ADDRESS (n)

BUS ACTIVITY:

MASTER

BUS ACTIVITY:

A

C

K

A

C

K

A

C

K

DATA n + 1

A

C

K

DATA n + 15

A

C

K

S

A2

B0

A1 A0 B2 B1

5.0

ACKNOWLEDGE POLLING

Since the device will not acknowledge during a write

cycle, this can be used to determine when the cycle is

complete (this feature can be used to maximize bus

throughput). Once the stop condition for a write com-

mand has been issued from the master, the device ini-

tiates the internally timed write cycle. ACK polling can

be initiated immediately.

This involves the master

sending a start condition followed by the control byte for

a write command (R/W = 0). If the device is still busy

with the write cycle, then no ACK will be returned. If the

cycle is complete, then the device will return the ACK

and the master can then proceed with the next read or

write command. See Figure 5-1 for flow diagram.

FIGURE 5-1:

ACKNOWLEDGE POLLING

FLOW

6.0

WRITE PROTECTION

The 24AA164 can be used as a serial ROM when the

inhibited and the entire memory will be write-protected.

Send

Write Command

Send Stop

Condition to

Initiate Write Cycle

Send Start

Send Control Byte

with R/W = 0

Did Device

Acknowledge

(ACK = 0)?

Next

Operation

NO

YES