24AA164

DS21100F-page 7

© 1999 Microchip Technology Inc.

7.0

READ OPERATION

Read operations are initiated in the same way as write

operations with the exception that the R/W bit of the slave

address is set to one. There are three basic types of read

operations: current address

read, random read, and

sequential read.

7.1

Current Address Read

The 24AA164 contains an address counter that maintains

the address of the last word accessed, internally incre-

mented by one. Therefore, if the previous access (either a

read or write operation) was to address n, the next current

address read operation would access data from address n

+ 1. Upon receipt of the slave address with R/W bit set to

one, the 24AA164 issues an acknowledge and transmits

the 8-bit data word. The master will not acknowledge the

transfer but does generate a stop condition and the

24AA164 discontinues transmission (Figure 7-1).

7.2

Random Read

Random read operations allow the master to access any

memory location in a random manner. To perform this

type of read operation, first the word address must be set.

This is done by sending the word address to the 24AA164

as part of a write operation. After the word address is sent,

the master generates a start condition following the

acknowledge. This terminates the write operation, but not

before the internal address pointer is set. Then the master

issues the control byte again but with the R/W bit set to a

one. The 24AA164 will then issue an acknowledge and

transmits the 8-bit data word. The master will not acknowl-

edge the transfer but does generate a stop condition and

the 24AA164 discontinues transmission (Figure 7-2).

7.3

Sequential Read

Sequential reads are initiated in the same way as a ran-

dom read except that after the 24AA164 transmits the

first data byte, the master issues an acknowledge as

opposed to a stop condition in a random read. This

directs the 24AA164 to transmit the next sequentially

addressed 8-bit word (Figure 7-3).

To provide sequential reads the 24AA164 contains an

internal address pointer which is incremented by one at

the completion of each operation. This address pointer

allows an entire device memory contents to be serially

read during one operation.

7.4

Noise Protection

is below 1.5 volts at nominal conditions.

The SCL and SDA inputs have Schmitt trigger and filter

circuits which suppress noise spikes to assure proper

device operation even on a noisy bus.

FIGURE 7-1:

CURRENT ADDRESS READ

FIGURE 7-2:

RANDOM READ

FIGURE 7-3:

SEQUENTIAL READ

CONTROL

A

C

K

S

T

A

R

T

S

T

O

P

BYTE

DATA n

BUS ACTIVITY

MASTER

SDA LINE

BUS ACTIVITY

A

C

K

N

O

S

1 A2 A1 A0 B2 B1 B0

P

S

P

S

BUS ACTIVITY

MASTER

SDA LINE

BUS ACTIVITY

S

T

A

R

T

S

T

O

P

CONTROL

BYTE

A

C

K

WORD

ADDRESS (n)

CONTROL

BYTE

S

T

A

R

T

DATA (n)

A

C

K

A

C

K

N

O

A

C

K

1A2 A1A0B2B1B0

P

BUS ACTIVITY

MASTER

SDA LINE

BUS ACTIVITY

S

T

O

P

CONTROL

BYTE

A

C

K

N

O

A

C

K

DATA n

DATA n + 1

DATA n + 2

DATA n + X

A

C

K

A

C

K

A

C

K