UPD780208 datasheet(74/472 Pages) NEC

74 / 472 page

Chapter 3

CPU Architecture

User’s Manual U16504EE1V1UD00

3.4 Operand Address Addressing

The following methods are available to specify the register and memory (addressing) which undergo

manipulation during instruction execution.

3.4.1 Implied addressing

The register which functions as an accumulator (A and AX) in the general register is automatically

(implicitly) addressed.

Of the µPD780828A Subseries instruction words, the following instructions employ implied addressing.

Operand format

Because implied addressing can be automatically employed with an instruction, no particular operand

format is necessary.

Description example

In the case of MULU X

With an 8-bit x 8-bit multiply instruction, the product of A register and X register is stored in AX. In this

example, the A and AX registers are specified by implied addressing.

Table 3-6:

Implied Addressing

Instruction

MULU

A register for multiplicant and AX register for product storage

DIVUW

AX register for dividend and quotient storage

ADJBA/ADJBS

A register for storage of numeric values which become decimal correction targets

ROR4/ROL4

A register for storage of digit data which undergoes digit rotation

UPD780208 Datasheet(PDF) 74 Page - NEC