COP8-REF-AM datasheet(58/83 Pages) NSC

58 / 83 page

18.0 Interrupts (Continued)

enabled; if the pending bit is already set, it will immediately

trigger an interrupt. A maskable interrupt is active if its asso-

ciated enable and pending bits are set.

An interrupt is an asychronous event which may occur be-

fore, during, or after an instruction cycle. Any interrupt which

occurs during the execution of an instruction is not acknowl-

edged until the start of the next normally executed instruc-

tion. If the next normally executed instruction is to be

skipped, the skip is performed before the pending interrupt is

acknowledged.

At the start of interrupt acknowledgment, the following ac-

tions occur:

The GIE bit is automatically reset to zero, preventing any

subsequent maskable interrupt from interrupting the cur-

rent service routine. This feature prevents one maskable

interrupt from interrupting another one being serviced.

The address of the instruction about to be executed is

pushed onto the stack.

The program counter (PC) is loaded with 00FF Hex,

causing a jump to that program memory location.

The device requires seven instruction cycles to perform the

actions listed above.

If the user wishes to allow nested interrupts, the interrupts

service routine may set the GIE bit to 1 by writing to the PSW

the current service routine. If nested interrupts are allowed,

caution must be exercised. The user must write the program

in such a way as to prevent stack overflow, loss of saved

context information, and other unwanted conditions.

The interrupt service routine stored at location 00FF Hex

should use the VIS instruction to determine the cause of the

interrupt, and jump to the interrupt handling routine corre-

sponding to the highest priority enabled and active interrupt.

Alternately, the user may choose to poll all interrupt pending

and enable bits to determine the source(s) of the interrupt. If

more than one interrupt is active, the user’s program must

decide which interrupt to service.

Within a specific interrupt service routine, the associated

pending bit should be cleared. This is typically done as early

as possible in the service routine in order to avoid missing

the next occurrence of the same type of interrupt event.

Thus, if the same event occurs a second time, even while the

first occurrence is still being serviced, the second occur-

rence will be serviced immediately upon return from the

current interrupt routine.

An interrupt service routine typically ends with an RETI

instruction. This instruction set the GIE bit back to 1, pops

the address stored on the stack, and restores that address to

the program counter. Program execution then proceeds with

the next instruction that would have been executed had

there been no interrupt. If there are any valid interrupts

pending, the highest-priority interrupt is serviced immedi-

ately upon return from the previous interrupt.

Note: While executing from the Boot ROM for ISP or virtual

E2 operations, the hardware will disable interrupts from oc-

curring. The hardware will leave the GIE bit in its current

state, and if set, the hardware interrupts will occur when

execution is returned to Flash Memory. Subsequent inter-

rupts, during ISP operation, from the same interrupt source

will be lost.

18.3 VIS INSTRUCTION

The general interrupt service routine, which starts at address

00FF Hex, must be capable of handling all types of inter-

rupts. The VIS instruction, together with an interrupt vector

table, directs the device to the specific interrupt handling

routine based on the cause of the interrupt.

VIS is a single-byte instruction, typically used at the very

beginning of the general interrupt service routine at address

00FF Hex, or shortly after that point, just after the code used

for context switching. The VIS instruction determines which

enabled and pending interrupt has the highest priority, and

causes an indirect jump to the address corresponding to that

interrupt source. The jump addresses (vectors) for all pos-

sible interrupts sources are stored in a vector table.

The vector table may be as long as 32 bytes (maximum of 16

vectors) and resides at the top of the 256-byte block con-

taining the VIS instruction. However, if the VIS instruction is

at the very top of a 256-byte block (such as at 00FF Hex),

the vector table resides at the top of the next 256-byte block.

Thus, if the VIS instruction is located somewhere between

00FF and 01DF Hex (the usual case), the vector table is

located between addresses 01E0 and 01FF Hex. If the VIS

instruction is located between 01FF and 02DF Hex, then the

vector table is located between addresses 02E0 and 02FF

Hex, and so on.

Each vector is 15 bits long and points to the beginning of a

specific interrupt service routine somewhere in the 32-kbyte

memory space. Each vector occupies two bytes of the vector

table, with the higher-order byte at the lower address. The

vectors are arranged in order of interrupt priority. The vector

of the maskable interrupt with the lowest rank is located to

0yE0 (higher-order byte) and 0yE1 (lower-order byte). The

next priority interrupt is located at 0yE2 and 0yE3, and so

forth in increasing rank. The Software Trap has the highest

rand and its vector is always located at 0yFE and 0yFF. The

number of interrupts which can become active defines the

size of the table.

Table 33 shows the types of interrupts, the interrupt arbitra-

tion ranking, and the locations of the corresponding vectors

in the vector table.

The vector table should be filled by the user with the memory

locations of the specific interrupt service routines. For ex-

ample, if the Software Trap routine is located at 0310 Hex,

then the vector location 0yFE and -0yFF should contain the

data 03 and 10 Hex, respectively. When a Software Trap

interrupt occurs and the VIS instruction is executed, the

program jumps to the address specified in the vector table.

The interrupt sources in the vector table are listed in order of

rank, from highest to lowest priority. If two or more enabled

and pending interrupts are detected at the same time, the

one with the highest priority is serviced first. Upon return

from the interrupt service routine, the next highest-level

pending interrupt is serviced.

If the VIS instruction is executed, but no interrupts are en-

abled and pending, the lowest-priority interrupt vector is

used, and a jump is made to the corresponding address in

the vector table. This is an unusual occurrence and may be

the result of an error. It can legitimately result from a change

in the enable bits or pending flags prior to the execution of

the VIS instruction, such as executing a single cycle instruc-

tion which clears an enable flag at the same time that the

pending flag is set. It can also result, however, from inad-

vertent execution of the VIS command outside of the context

of an interrupt.

COP8-REF-AM Datasheet(PDF) 58 Page - National Semiconductor (TI)

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