ZL38002

Data Sheet

13

Zarlink Semiconductor Inc.

Figure 6 - ST-BUS and GCI 16-Bit 2’s Complement Linear PCM I/O (Mode 4)

2.2

SSI Operation

The SSI PCM interface consists of data input pins (Rin, Sin), data output pins (Sout, Rout), a variable rate bit clock

(BCLK), and two enable pins (ENA1, ENA2) to provide strobes for data transfers. The active high enable may be

either 8 or 16 BCLK cycles in duration. Automatic detection of the data type (8 bit companded or 16-bit 2’s

complement linear) is accomplished internally. The data type cannot change dynamically from one frame to the

next.

PORT1

Rin/Sout

ST-BUS/GCI Mode

Selection

PORT2

Sin/Rout

Enable Pins

Enable Pins

MD1

ENA1

MD2

ENA2

0

0

Mode 1. 8 bit companded PCM I/O on timeslot 0

0

0

0

1

Mode 2. 8 bit companded PCM I/O on timeslot 2.

0

1

1

0

Mode 3. 8 bit companded PCM I/O on timeslot 2.

Includes D & C channel bypass in timeslots 0 & 1.

10

1

1

Mode 4. 16-bit 2’s complement linear PCM I/O on

timeslots 0 & 1.

11

Table 2 - ST-BUS & GCI Mode Select

C4i

F0i (stbus)

Rin

Sout

76 5 4 3210

Sin

Rout

PORT1

PORT2

S 1413 12 11 10 9 8

ST-BUS/GCI Mode 4 allows 16 bit 2’s complement linear data to be transferred using ST-BUS/GCI I/O timing. Note that PORT1 and

PORT2 need not necessarily both be in mode 4.

outputs = High impedance

inputs = don’t care

76 5 4 3210

S1413 12 11 10 9 8

76 5 4 3210

S1413 12 11 10 9 8

76 5 4 3210

S 1413 12 11 10 9 8

F0i (GCI)

start of frame (stbus & GCI)

EC

EC